Introduction

Within electronic design automation, logic verification has become the number one bottleneck as increasing design complexity results in an exponential rise in the verification time using traditional logic verification techniques. This situation is only exacerbated by the emerging trend toward system-on-chip (SoC) ASICs. A confluence of Moore’s Law and advances in semiconductor processing techniques has brought us to a point where digital logic, memory and mixed-signal digital/analog logic can be combined on the same silicon die. Thus, yesterday’s systems which included several ICs on a printed circuit board (PCB) can now be integrated on a single chip. The task of verifying these very complex SoC ASICs with traditional techniques is difficult.

The product development cycle is broken down into four areas: creation, analysis, real-world validation and production. (See Figure 1)

Figure 1 - Development Cycle of a Complex Embedded System

Verification tools have been evolving in parallel with the design creation process. As designs have become more complex, the simulators simply run too slow to meaningfully verify complex designs at the detailed, gate-level of design description. Consequently, logic simulators, like design creation tools, have evolved to work on more abstract design descriptions. Even hardware simulation accelerators which evolved in the mid-1980s are considered too slow, and have the additional drawback of requiring the creation of manually developed test programs for verification. Since developing design and test specifications is never a perfect or complete process, any design ultimately needs to be validated in a real-world environment at the system level to determine if it performs as expected.

Figure 2 - Comparison of Performance of Verification Solutions

ASIC emulation has been evolving since the end of the 1980s as a technology using hardware to mimic custom logic design to meet the need to achieve real world verification. Companies focused on ASIC emulation typically emulate the custom logic of an ASIC by mounting large numbers of FPGAs in fixed arrays on printed circuit boards. Such systems can require lengthy development periods resulting in the use of FPGA components which can be generations behind the technology at the time of product release. In the mid-1990s, reconfigurable prototyping was introduced by Aptix to overcome the ease-of-use, cost and performance limitations of ASIC emulation, and to meet the evolving needs of system-on-chip designs.

Drive for Increased Chip-level Intellectual Property (IP) Integration

Integrated circuit technology advances are enabling electronic system designers to take functionality which previously required multiple integrated circuits and place it within a single ASIC. This system-on-chip technology is enabling the consumer, communications, and computer markets to converge, producing a whole new class of products. SoC designs require new levels of integration and testing prior to release for fabrication which creates new challenges for engineers. These designs typically include microprocessors, microcontrollers or digital signal processing functions that run considerable software within the SoC component. The building blocks, or intellectual property for SoC designs are being developed and licensed by independent third parties (fabless, chip-less semiconductor companies), traditional ASIC companies, EDA vendors, and internal design teams in company wide initiatives to leverage "design reuse".

Verification Methodology

Electronic systems are designed in stages, beginning with high-level algorithm development, evolving the design into blocks, and then translating functional blocks into hardware and software elements. Each block level element must be designed and verified at its most detailed level, and ultimately, the entire system must be validated in a real-world environment to assure functionality.

Engineers create designs in blocks of logic, typically smaller than 25,000 logic gates in complexity. This is limited both by the capacity of engineers to manage and track design elements effectively, and practical limitations of the logic synthesis tools used to produce optimized, detailed designs from the design descriptions. The latest ASIC emulation products introduced in mid-1998 use FPGAs that only hold about one-fourth of a typical design block created by an engineering team. The result is that each block must then be spread across multiple FPGAs. The costs of ASIC emulation systems are relatively high and the operating speeds are very low relative to what is possible with current, larger FPGAs. Since the third quarter of 1997, FPGAs used to prototype the custom logic of an ASIC design have become larger than the individual blocks of a design. This technology shift in the key building block of prototyping systems enabled a new block-based prototyping methodology that closely parallels the natural product development process. The importance of block-based prototyping methodology is as follows:

• it intuitively parallels the design creation process employed by most design teams;
• the methodology provides a mechanism to map and verify design blocks to prototype incrementally and in parallel with the design creation process;
• the verification process is simplified by avoiding time consuming, counter-intuitive partitioning processes of ASIC emulators which breakdown the designs natural block-based hierarchy and make debug and design iterations difficult and lengthy; and
• IP design reuse for system-on-a-chip ASICs is enabled.

A block-based prototyping methodology delivers the following customer benefits: (i) time-to-market advantages, (ii) cost effective solutions, (iii) real-world validation, and (iv) improved quality products.

Time-to-Market Advantages

With the block-based prototyping methodology, design preparation time is short, and real world validation can begin within days after the completion of the design. The reprogrammability of the hardware allows design iterations to be made quickly so the results of design changes can be evaluated quickly. As each block of a design is created and verified in the design creation environment, it can be independently mapped directly to the modules which will represent the design block in the system prototype. The block is then verified running the appropriate test program and then ready for use in the full system prototype or to be archived for use on other projects.

Reconfigurable system prototyping provides real-world validation benefits across the design process:

• Algorithm validation: new algorithms can be quickly implemented in hardware in the Aptix prototyping environment and tested in a real system environment.
• System integration: system software and hardware are integrated early in the development process, often before the entire design is complete. Without system prototyping, software debug cannot begin until all the hardware components are built and tested.
• Application validation: the entire system is run in its natural environment, importing and producing its natural data types.

This incremental approach to creating the prototype reduces the time to go in-circuit with the full prototype to the few days that it takes to verify the mapping of the last block. This contrasts with the many weeks to months it can take for ASIC emulation to achieve in-circuit operation because traditional emulation must first wait for the completion of the entire design and then uses block-flattening partitioning techniques to try to map the entire design all at once.

Figure 3-Traditional Design Process Flow

Figure 4- Process With Prototyping

Cost Effective Solutions

Open product architectures are required to allows designers to prototype their designs utilizing the largest and fastest FPGAs, IP blocks and off-the-shelf system components. This minimizes the complexity of the system prototype in terms of the number of FPGAs required to represent the system’s custom logic and minimizes the cost of the prototyping systems required to contain the FPGAs and other prototype elements.

Real-World Validation

Open architectures which optimize prototyping resources produce the highest performing verification speed short of fabricating the actual systems. Operating frequencies in the 20-35MHz range can be realized if prototypes are contained in a single or small number of circuit boards. Prototyping speeds increase as new IC technologies are incorporated into the commercial FPGA and system components. The result is that for many applications the prototype will run at real-time speed. For cellular or cordless phone applications, calls can be made on the prototypes configured in this manner. For industrial control applications, real equipment can operate. For applications where the prototype speed is less than actual product speed, the process of buffering input and output data to interface to the real world is significantly easier than with slower ASIC emulation systems.

Improved Quality System-on-Chip Products

System prototyping platforms separate the various design components into physical hardware blocks and provide visibility of all component pins, and the internal workings of custom logic in FPGAs. By combining visibility into a design with reprogrammability of the prototype, the hardware and software can be debugged, modified and retested all prior to fabrication of the first components.

Summary

The world of system design is quickly moving toward implementation of system-on-chip ASICs. The key issue in developing SoC ASICs will be validation of the system design prior to tape-out. Reconfigurable system prototyping using a block-based methodology parallels the design process and provides the flexibility and cost effectiveness to provide a realistic solution for the large number of projects expected to take the SoC approach.

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