This is a summary of the "SEU Mitigation Techniques for Virtex FPGAs in Space Applications" article. Click here to see the entire article.

SEU Mitigation Techniques for Virtex FPGAs in Space Applications

Carl Carmichael³
Earl Fuller², Phil Blain¹, Michael Caffrey¹
¹Los Alamos National laboratory
²Novus Technologies, Inc.
³Xilinx, Inc.

SRAM based logic devices such as FPGAs have some susceptibility to SEU and functional interruption. This paper describes several reliable mitigation techniques for the Virtex series FPGA architecture, which will retain functional integrity while static upsets are detected and corrected.

Additionally, this paper demonstrates how an SEU in an FPGA can be corrected in 3us without disrupting operation of the device, how to build hardened voting circuits, and that a single event has only 1 chance out of 3.25 million of causing a functional interrupt.

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