Martin S. Won, Member of the Technical Staff, Altera Corporation <mwon@altera.com>

Bernie Rosenthal, Vice President, Marketing & Business Development, Tensilica Inc. <bernier@tensilica.com>

The demand for systems designers to create products with higher functionality, more integration, in less time and at lower cost has never been greater. Such conditions, combined with advances in device technology, have led to an era where entire systems can be implemented on a single chip. Programmable logic has played a foundational role in this development, allowing designers to realize their designs in hardware much more quickly than if they had used custom solutions. Another advantage of programmable logic over other hardware solutions is the ability to maintain flexibility in the face of rapidly evolving technology standards, a phenomenon that has only increased over time, and shows no signs of disappearing. Other hardware solutions, including ASICs and assignment-specific programmable products (ASPPs) lack this flexibility. In terms of cost, programmable logic device costs have decreased at a greater rate than ASICs have, and despite the per-device cost advantage of ASICs, the shortening of product lifecycles means that many systems never reach the stage where an ASIC version is attractive. Often, a company’s valuable engineering resources are allocated to developing the next generation product, rather than trying to eke out cost savings on an existing product which may have passed its prime earning potential.

Many of the same factors that make programmable logic ideal for system-level design are also driving and shaping the growing intellectual property (IP) industry. The need to develop increasingly larger systems in shorter time spans makes it attractive for designers to take advantage of another party’s expertise whenever practical. Also, the rapid evolution of technology means that fewer individuals can retain mastery over all of the technical aspects of a given system, making the expertise of these individuals, in the form of IP, much more valuable. Another attraction to IP use is that it promises an avoidance of the risk of investing internal resources to developing a custom solution in favor of adopting a ready-made solution that can be tailored to meet the need. Finally, the unique needs of each design and changing electronics standards means that flexibility is an increasingly desirable characteristic in IP, generally in the form of user configurability.

The IP industry emerged first from the ASIC arena where system-on-a-chip design first became a reality. But as programmable logic densities have risen and component costs decreased, programmable logic has become increasingly important to the IP industry. For example, the number of design starts in PLDs outnumbers the number in ASICs by an order of magnitude, indicating a much greater potential need among PLD users for IP. PLD design flows have also benefited from great advances in IP performance and customization. For example, it is now possible for a PLD user to choose from among several architecture-optimized IP offerings, configure that piece of IP to meet the specific needs of the design, and compile and simulate the complete design before making any commitment to license the IP. All of these steps can even take place without the involvement of the IP or PLD vendor, resulting in a very streamlined design evaluation process completely directed by the PLD user. The only step requiring the involvement of the IP vendor is licensing, and with the advent of electronic commerce, even this step need not take long,

Besides advances in development tools, PLD technology is moving towards system-level solutions in devices as well. The latest programmable logic includes large embedded memory structures, phase-locked loops, and support for a wide variety of I/O standards. With these features and capacity levels reaching into the millions of gates, programmable logic can accommodate a host of larger and more complex IP blocks. For example, a 64-bit PCI master/target bus interface occupies less than 10% of the logic resources in a 400,000-gate Altera APEX 20K400 device. In the same device, a 1024-point FFT with 16-bit data width occupies less than 20%, and a multi-standard adaptive pulse code modulation (ADPCM) function with support for 20 full-duplex channels requires about 25% of the logic resources. The current availability of multiple microprocessor cores for programmable logic is significant because they form the foundation of many system designs. One notable example, which combines great complexity with user configurability and extensibilty, is Tensilica's configurable embedded processor solution called Xtensa™.

Tensilica is the first IP company with a complete configurable microprocessor solution consisting of a processor core hardware description, and all of the associated embedded software development tools to facilitate the rapid generation of optimized custom hardware and software. Using its Xtensa architecture, the company focused on the application-specific extensibility of the core processor and on creating effective methods for hardware/software integration to optimize designs and speed time to market.

The Xtensa core, developed to serve the needs of a wide range of volume applications that are cost sensitive, space limited, power conscious and performance hungry, currently fits in a FLEX 10KA device, the EPF10K250A, which forms the hardware implementation of the Xtensa XT1000 evaluation kit (see Figure 1).

Figure 1: Block Diagram of Xtensa Processor implemented in a FLEX 10K Device on the XT1000 Emulation Board

In the FLEX 10K family, Xtensa uses Embedded Array Blocks (EABs) to implement a register file, illustrating the greater integrative capability of today’s embedded memory-enabled PLDs. Xtensa is also targeted for the new APEX family of devices, which will offer greater gate densities so that more feature rich processor cores and associated system elements can become a designer reality. These APEX-optimized versions could become available in the coming months.

The placement of a configurable microprocessor on a PLD is particularly significant because it furthers the co-development of hardware and software. Combined with programmable logic’s ability to quickly produce working hardware, use of customizable microprocessor and other cores means that designers can quickly create functioning, system-level designs in a fraction of the time it would take to produce the equivalent in an ASIC. With rapid production of working system-level designs, software development can proceed apace with real hardware, reducing the "hardware handoff to software" step of system development. Figure 2 shows a diagram of the difference between two design flows, one involving a custom ASIC solution, and another involving programmable logic.

Figure 2: System on a Programmable Chip Design Cycle vs. System on a Custom Chip Design Cycle

As the figure shows, even with an optional migration to a custom solution, the overall programmable logic flow cycle is much shorter than the ASIC design flow. The exact amount of time saved varies from design to design, but even for a design that is only in the tens of thousands of gates range, the savings can be on the order of months.

The digital design industry has witnessed an advance of programmable logic devices into the density realms once occupied only by ASICs. Many designs in the tens of thousands of gates range are being targeted at PLDs only, with no thought of an ASIC conversion, and the gate range "sweet spot" for PLDs designs is moving ever higher. Design development costs for PLDs will also decline much more quickly relative to ASICs, which continue to require large volume orders and high NREs, especially for the latest sub-micron processes.

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