ICT is a leader in Programmable Logic Device (PLD) technology and has participated in the PLD market for 18 years. ICT has invested in applying PLD capabilities to address current technical issues facing the System-On-Chip (SOC) semiconductor market. ICT is currently working with foundry partners to provide embedded PLD cores and core compilers for use in SOC devices.

ICT investment in embedded programmable logic

With the emergence of SOC devices as the foundation for more highly integrated electronic products, ICT has looked at the design process for SOC devices and at how programmable logic is used in conjunction with integrated SOC devices. The opportunities discovered from this analysis are presented below. ICT has invested in technology to enable on-chip re-configurable logic and non-volatile memory that are compatible with standard logic processes and tuned to the needs of SOC devices. ICT is also developing core compilers, programming tools and application development environments to provide complete design solutions. ICT will license this technology and embeddable cores to semiconductor manufacturers and SOC semiconductor providers.

ICT offerings in PLD cores and development environment

ICT is currently developing PLD cores with a major foundry partner. The first core will be available in Q1’ 2000. This core will contain 40 macro-cells and is compatible with the ICT PEEL Array device model PA9040. The core will provide in-circuit re-configuration and in-system testability through a JTAG port. Development software and configuration software are already available.

A PLD core compiler will be available in the second half of 2000. This software allows users to compile customized PLD core arrays optimized for a specific foundry and process. The user will have parameterized control of core features including number and type of macro-cells, number of inputs and number of logic terms per macro-cell.

According to the Dataquest, July 1999 report entitled "Worldwide ASIC/SLI Forecast: Spring 1999", The SOC market will grow from $9B in 1998 to $32B by 2003. The report also notes that the major markets that are served by SOC solutions are also growing rapidly. These are communications, primarily digital cell phones, consumer information appliances and data processing appliances including Digital Set-Top box, video games, and DVD players. One of the most noted issues of this SOC market is the escalating design complexity of SOC and the rapidly changing end markets for SOC enabled products. A key factor in mitigating the risk in complexity and time-to-market is identified as design reuse. To date, this has been accomplished by using pre-tested functional IP cores such as processor cores, DSP cores, graphics cores, etc. to provide block reuse. But an even more important factor for SOC success has been identified as device reuse to address evolving or multiple product requirements.

Currently, the benefits in cost-efficiency that SOC provide are somewhat offset by the long time-to-market in SOC development and the inability to customize the SOC functionality to provide product differentiation and adaptation to emerging requirements. It has been noted by many sources, including Dataquest, Lucent, LSI and other SOC manufacturers that there is a strong need to provide flexible SOC devices that enable OEMs to enter markets early while still providing the ability to differentiate features, and accommodate requirements changes that are typical of emerging markets.

ASPP market characterization

Dataquest has characterized SOC devices with embedded programmable logic as Application Specific Programmable Products. They forecast that ASPP has the potential to account for 80% of the SOC market within 10 years.

SOC devices and the design methodology for producing them are complicated and rapidly evolving. New start-up companies are focusing on the problems of co-development of hardware and software. The commerce of IP cores is slowly becoming viable. New companies are appearing to address the issues of on-chip integration busses and SOC prototyping tools. Major EDA companies are addressing the needs of SOC with hierarchical simulation environments, chip assembly flows, mixed signal design flows, design services and IP infrastructure. In general, this is an area that is evolving quickly enough so that the design methodology changes substantially from one device implementation to the next.

Complexity & size

SOC devices typically contain one or more processor cores (general purpose or DSP) along with their peripherals, busses and memory controllers. To this is added standard IP cores and proprietary IP cores. Software must be integrated with the silicon in order to realize the intended product functionality. The entire system must be validated to product requirements and optimized to provide competitive market features. The amount of time that must be spent in detailed simulation/emulation to perform this validation is inversely related to the ability to modify or repair the design post-silicon.

The value of IP to accelerate SOC design is based on the fact that it has been pre-validated to the particular application and is then used without change. For the SOC engineer, the design task is to successfully interface the IP core with the rest of the design and optimize and validate the interface.

One of the characteristics of consumer markets is rapid feature evolution. This is typically reflected in a product specification that changes multiple times throughout the design cycle. This is particularly true in communications products where the defining standards are evolved and refined by standards committees on an ongoing basis. The ability to complete the design process and deliver product early is greatly enhanced if programmability is included to enable feature refinements.

The promise of SOC is to rapidly assemble proven IP blocks into complete silicon based systems and then to optimize and customize the end products to multiple product opportunities. Today, the bulk of the development time is spent in tedious simulations of the logic against presumed requirements. This effort is ineffective at best but is justified because there is little or no option to repair problems or modify hardware interfaces that are not detected prior to silicon. Also, today, the ability to customize the performance or interface to changing requirements is not expected. The strategic inclusion of re-configurable logic can be directly traded against time-to-market by reducing the simulation burden and by allowing features to be added/tuned post-silicon.

In all cases for fixed logic, there is a small margin for error. With discrete functional ASIC or ASSP devices, PLDs have been used on the circuit board to fix problems in interface or to add customized logic that was not built in to the devices. For SOC devices, this issue will still remain, however, for consumer devices, space, power and cost are critical resources and adding external devices is impractical. Adding small amounts of re-configurable logic on-chip provide this capability to repair problems or add customization with minimal time and expense. For SOC devices this is even a stronger issue since many of the tunable interfaces are only available on-chip.

For the cases described above, there is a need for re-configurable logic to provide for logic repair, control circuit tuning, interface variation tuning, flexible IP "sockets". The re-configurable logic implements the control and interface circuits while the much larger IP cores and data path elements are implemented in fixed logic. Solutions for these applications do not require large arrays of programmable logic. Instead, multiple smaller blocks of re-configurable logic better address them. With this approach, the total requirement for on-chip re-configurable logic is less than 15,000 gates.

PLD cores are a best fit for most of the actual needs of SOC re-configurability.

In contrast, FPGA based approaches attempt to implement entire circuits including data-path in a large monolithic, re-configurable block.

Much simpler software than for FPGA

The software for programming, configuring and in-system testing of PLDs is also very simple and very mature. The PLD logic design process easily integrates into standard block authoring flows.

In contrast, the software for mapping logic and routing interconnect for FPGA is extremely complex. The debug process must take into account potential place and route software bugs, possible timing marginality as well as user logic problems. Given that each embedded FPGA block may be unique in some way, the likelihood of software bugs is very high. Adding this into an already complex SOC with limited internal visibility and integrating this design and debug process into the rest of the design flow would be problematic.

The PLD design process is well matched with standard design environments and easily integrated into an embedded environment.

Because of the well-constrained programmability and deterministic behavior, debug and verification are inherently straightforward. The addition of in-circuit re-configurability and in-system testability make this a very good way to view and characterize other parts of the design as well.

One of the strongest values of embedded PLD re-configurable logic is the ability to make repairs with minimal effort and risk in areas that are anticipated (e.g. interface handshakes) but also the potential to make repairs in areas that were not predicted with only minor time and cost impact. It is anticipated that a full mask set for a 12-inch wafer will be upwards of $500K. Providing a capability of repairing a circuit is of enormous value.

PLD cores with non-volatile cells only need to be re-configured when the configuration changes, which is a very rare occurrence. FPGA cores are typically SRAM based and have to be re-configured on every power cycle and hard device reset.

The stable program feature of PLD cores can increases reliability in a number of areas.

• Eliminate an external memory device and interface
• Retains configuration and eliminate or greatly reduce programming events
• PLD cores are not modified during device power-up or hard reset initialization activities

ICT will provide fixed embedded PLD core structures that are similar to the discrete devices. This will lever the existing knowledge and more importantly the proven software and the interfaces to third party tools. The roadmap for the development of fixed cores will be determined with partners.

The core compiler will allow designers to customize the PLD core to match specific circuit requirements.

At right is a diagram of the basic compiled PLD core structure.

The basic compiled PLD core consists of a user-specified number of Configurable Logic Building Blocks (CLBBs). Within the CLBB the user can also configure aspects such as: number of macro cells (up to 16), number of inputs, number of product terms, number of clocks, register behavior and feedback options.

A Configurable Interconnect Multiplex Matrix (CIMM) provides flexible connection between on-chip signals to the PLD array.

Alternately, IO signals can bypass the CIMM block where fixed connection requirements are known.

Initial version of the compiler will support re-configurable blocks with up to 16 CLBBs. The focus on the initial compiler will be on required features and ease-of -use within existing design environments. ICT will provide a compiler roadmap to integrate additional capabilities over time.

In cases where a much larger re-configurable logic core is desired, the ICT core compiler provides the option for expansion of the core by extending the interconnect matrix hierarchically. The Configurable Global Interconnect Multiplex Matrix (CGIMM) provides scalable interconnect while maintaining deterministic signal timing and compact area.

PLD cores are re-configurable through a serial in-circuit re-programming interface.

Within the core compiler, the designer can specify the level of re-programmable access that is supported for each core. Manufacturer re-configurability supports interface tuning device configuration and device repair OEM re-configuration supports security codes, feature selection, product upgrades and repair. Open re-configuration provides application configuration and status retention.

The Scalable On-Chip Re-Configurable Logic Engine (SCORE™ ) Compiler drives the design and configuration of the programmable system. This engine takes user’s design and constraint inputs and technology library, which includes different views of CLBB and CIMM, and then generates the programmable logic IP with proper structure and size. The SCORE Compiler also generates several outputs, which provide netlist, timing parameters, simulation model, and layout information specific to the IP core. These output files are in industry standard formats and work with third party design tools and methodology.

Below are some application areas where small re-configurable blocks of logic and non-volatile memory provide very large return in SOC based products.

ICC Programmability-On-Demand™ PLD cores and non-volatile memory cores allow designers to optimize and verify product requirements in-system and in real-time. They also allow designers to deliver and validate differentiating features with very low risk. This Self-Prototyping™ capability reduces the simulation burden for SOC verification and reduces the need for pre-silicon prototyping environments. This results in a faster, less expensive, more robust SOC product design process.

ICT Programmability-On-Demand™ PLD cores and Non-volatile memory cores provide integrated capability to store security and configuration information. This eliminates the risk and cost of external security memory and provides novel options for secure algorithms and feature access control.

Programmable interfaces can increase SOC device reuse by enabling SOC devices to adapt to multiple product requirements and to evolving product requirements.

Programmable interfaces can allow manufacturers to reduce the delay from standard protocol adoption to consumer product delivery to the market. This applies, for example, to all of the emerging communications standards. ICT Programmability-On-Demand™ cores can allow designers to accommodate the impact of final changes in the standard within re-configurable logic, so that products can be prepared in advance of final standard adoption. Product verification and type approval can begin as soon as the standard is ratified.

With IP-based design, there are opportunities to differentiate product performance through optimized interface design. The interface circuitry typically involves hardware handshakes, data and clock synchronization and resource arbitration. The logic required to tune these interfaces is generally very small, in the hundreds of gates.

Verifying and tuning the performance at the product level involves interaction with software and other external entities that is most effectively tuned in-system and at real-time. ICT Programmability-on-Demand™ PLD cores provide the ability to ‘prototype’ these interfaces with re-configurable logic at real-time to optimize and fix the performance for real-system constraints.

"Fix-It" blocks to allow device repair

The greatest weakness with system level integration and SOC devices is the inability to repair the hardware or adapt it to fit new requirements. Redesign cost and new mask sets can be impossibly high for even the simplest fix. Traditionally, for less integrated solutions, PLD devices have been used to effect repairs on the board. SOC devices reduce access to the necessary signals and consumer product miniaturization and cost sensitivity take away this proven technique. ICT Programmability on Demand™ PLD cores can provide the ability to repair internal hardware problems with little or no time and cost impact.

The value in IP cores is realized from reuse without modification. The design approach involves building "sockets" for the IP cores to "plug" into. In this scenario the vast majority of the logic would be fixed in place while a small portion of the socket logic would be re-configurable. This provides the flexibility to cover risk and to tune performance while greatly reducing the design time and effort.

ICT is committed to the SOC market and to providing practical re-configurable solutions matched to SOC needs. We will continue to offer new features for re-configurable SOC as the capabilities evolve and mature. Following on our non-volatile memory compiler and our embedded PLD compiler, will work with partners to develop this roadmap.