Modern ASIC (Application Specific Integrated Circuit) devices are staggering in their complexity and increasingly expensive to manufacture. It is no surprise then that verification is built-in as an integral part of the design methodology for these devices. When it comes to verification, the cost of making a mistake is much lower in a PLD since they can be re-programmed on a designerýs desktop. As a result most PLD designers are just now beginning to adopt the newer verification techniques used by their ASIC counterparts. The growing PLD gate-densities seem to be driving this change.

An increasing percentage of PLD designs are designed using an abstract high-level description language (VHDL or Verilog HDL) which starts by describing the intended behavior of the circuit. This high-level description of the circuit is then synthesized to gates and finally place-and-routed in a specific PLD.

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