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This is an abstract of the "Configurable Logic for Digital Communications" article. Click here to see the entire article.

 

An Open System Approach For Verilog and VHDL Debugging

Scott Sandler

For today's complex ICs, ASICs, and SoCs, debugging is more costly than verification. Verification, which determines the existence of bugs, can be put in the background as a batch job or accelerated by running many jobs in parallel. In contrast, the interactive nature of debuggingıthe process of understanding the reasons for the defectsırequires the continuous direct involvement of an engineer. Consequently, debugging costs are not limited to software and hardware. The cost of debugging must necessarily include engineering time, and more importantly, the opportunity cost incurred every moment an engineer is tracking down old problems instead of adding new product value.

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