By Brian Faith (faith@quicklogic.com) and Mao T. Wang

Customer Engineers

QuickLogic Corporation

Design engineers who create embedded PC products have unique system size, power, performance and feature requirements. To address these requirements, companies such as QuickLogic developed a new device approach, called Embedded Standard Products (or ESPs). These devices integrate system-level building blocks, such as PCI controllers, with large amounts of programmable logic and on-chip SRAM. With this approach, we provide single-chip solutions for several applications, saving board space, reducing power consumption, and lowering system costs.

The Standard Product functionality and increasing densities QuickLogic provides with ESP devices enable engineers to adopt an ASIC-like design methodology. One approach ASIC designers are now emphasizing is design reuse. Towards this end, QuickLogic provides Verilog and VHDL cores that interface with the embedded functionality of ESP devices. These "soft" cores allow customers to include additional functionality in QuickLogic ESP devices, with minimal engineering cost.

All of the "soft" cores that QuickLogic provides follow industry standard design reuse guidelines, which will be highlighted in this paper. These reusable cores benefit the designer by providing well-documented HDL that can be easily ported to other designs, and possibly to an ASIC. To illustrate several design reuse principles, a case study was performed. The case study shows how QuickLogic’s QuickPCI devices can be used in a CardBUS system by implementing a small "soft" core add-on to the existing PCI embedded standard product functionality.

In today’s electronic systems, performance and feature requirements have greatly grown in complexity. Furthermore, in order for design engineers to keep up with ever-changing market demands they have to be able to release products as fast as possible.

To address these issues, today’s engineers cannot afford to spend a lot of time recreating standard functions and previously created parts that are available to them in the market a low cost. They need to be able to leverage designs previously created within the same company or by themselves and use it in the current development of their new products.

Maximizing intellectual property reuse is the only way to address these requirements. It allows design engineers to use their time very efficiently, by creating designs by integrating building blocks, putting together previously created reusable designs in the form of soft-cores, acquiring them through external vendors, adopting ASIC-like design methodologies.

Companies such as Quicklogic have developed a new approach, called Embedded Standard Products (or ESPs). These devices combine the best of both worlds, customizable standard products and programmable logic. This approach allows the designer to integrate system-level building blocks, such as customizable PCI controllers along with soft-cores or custom designs in the FPGA side of the chip. With this approach, Quicklogic provides a single-chip solution to many of today’s applications needs, and offers many advantages over other design approaches including saving board space, reducing power consumption, reducing design time and reducing overall system design costs.

We will use a case study to show how easily a design using Quicklogic’s ESPs with many reusable soft-cores can be easily ported into other designs. The case study shows how Quicklogic’s QuickPCI ESP devices can be used in a CardBUS system by implementing a small soft core add-on to the existing customizable PCI embedded standard product functionality.

We will begin by explaining the concept of design reuse, showing the available options for design reuse, and then explaining how to choose the approach that maximizes design efficiency for a particular case.

So, what is design reuse? Design reuse is a very simple concept; namely to design by putting together system level blocks, and document their functionality for future use. Ideally, reusable designs are portable to any technology, easily configurable or scalable and very easy to use. Design reuse has been used in big companies for a very long time. Design engineers need to follow a defined methodology, so other design engineers in the same organization can be able to reuse a design or to continue to work on designs created by previous engineers.

There are three types of reusable IP: soft, hard and firm.

A "soft macro" is a synthesizable set of RTL code in an industry standard HDL such as Verilog or VHDL.

A "hard macro" is a GDSII file, which is fully designed, placed and routed by the designer.

A "firm macro" is a mix of the above mentioned soft and hard macro, it is a soft core that has been pre-placed and routed.

A truly reusable design works in multiple technologies. It should be simulatable in a variety of simulators, verified to a high level of confidence independent of the chip in which it will be used and it has to be fully documented. The problem that arises is that a soft, hard or firm macro, cannot completely meet the ideal definition of a design reuse.

A soft macro cannot be verified with a high level of confidence independently of the chip, because of its performance and timing issues are completely different depending on the target chip. Soft IP presents many obstacles. For instance, mapping a complex soft IP function onto a particular silicon platform often presents enormous challenges from the standpoint of performance, internal timing, size, silicon cost, routability and pin-out stability. Another obstacle is that soft IP functions cannot address the specialized physical interface requirements of many applications. Finally, when these technical obstacles are combined with the complex business issues of licensing fees, royalty payments and technical support, implementing designs with third party soft IP often becomes an impossible task.

A hard macro does not support compatible to multiple technologies. Therefore, these macros only get close to the ideal definition of design reuse, so it is possible that a combination of these with other approaches would yield to a better solution. Hard IP functions provide a layout for a specific process technology optimized for performance, power and area. Hard cores solve the predictability problems associated with soft cores but at a significantly higher cost. The core itself is fixed, eliminating the ability of the user to modify the design.

Firm IPs, on the other hand, consist of soft-core functions that have been pre-placed and routed. In other words, the basic design topology has been established in advance. Firm cores provide a hybrid approach that offers some advantages in flexibility relative to hard cores. The developer of a firm core can more quickly release revisions that provide new features, improved performance and support additional silicon devices. From a physical device standpoint, the firm core typically offers higher performance and is more reliable than the soft IP approach because the designer still has control over component placement and routing paths.

It is not at all clear, however, that firm cores provide significant advantages in customizability relative to soft cores. Since the device has been routed, even the smallest changes have the risk of adversely affecting performance and timing. Changes are relatively difficult and expensive and usually must be left to the designer of the core. In addition, because the designer is still not working at the silicon level, the efficiency and performance are considerably lower and the cost higher than other approaches. Finally, firm IP does not address the specialized IO requirements needed in many of today’s applications.

A revolutionary approach is the ESP approach. The ESP approach includes a standard product, which is a pre-designed and customizable core that is fully compliant with an industry standard, such as IEEE, ANSI, etc. with programmable logic and the interface between them. The programmable logic portion of the chip allows the user to take advantage of soft macros or create fully custom designs. This solution is a unique interpretation to design reuse concept and does maximize it. It allows the designer to customize the standard core to their needs and use the programmable to implement previously created soft macros. This approach, for example, makes the migration of a PCI core to a CardBUS core very easy, by customizing the PCI core and adding soft macros in the programmable side, designers can leverage: reuse functions already done before.

Using reusable IP further enhances the advantage of using ESPs in a design. A reusable IP block in the form of a soft core, or written in a standard hardware description language such as VHDL or Verilog is portable and very flexible and so can be used to target any technology.

Fast Time to Market. This is especially helpful in creating designs using previously designed IPs. The design process becomes like building blocks design, by using existing designs. This process speeds up the design time and also avoids the need of spending time working on a design several times.

Single Chip Design. Using IPs with an ESP optimizes a design in terms of speed, timing issues and size in a relatively short amount of design time. It allows the design engineer to create within a single chip many features that it would require many IC chips to create when using other design approaches.

Application Alternatives. One viable arrangement is to route some embedded memory space on the FPGA to the PCI controller over one bus and use that to control the other two buses — one running from the FGPA to the PCI core and the other in the opposite direction. This arrangement provides order of magnitude increases in throughput compared to the fastest existing PCI controller designs. As a result, it provides enormous benefits to data communications, networking and video applications that can make use of this bandwidth. This approach also provides substantial reductions in cost and board space because it integrates functions that today require three or four discrete devices — the PCI controller, FIFO, FPGA and glue logic — into a single IC. Separate 64-bit buses could also be routed from the FPGA to different peripherals. An embedded controller could even be located on the opposite side of the FPGA.

Security. Designing an ESP with reusable IPs is also very secure. Once the IP is place and routed in the ESP and programmed into a chip, it is impossible to get the design back, therefore protecting the IP from design theft.

Design Flexibility. Design flexibility is high since the user can completely control the configuration of the FPGA and has the ability to extensively modify the FPGA. The availability of 360-plus interface signals is far more than current PCI controllers, which typically have about 70 interfaces. In addition, lane shifters are provided for unaligned transfers as well as separate byte lane controls for target pre-fetching. Signals are also provided from all FIFOs indicating their present status. This provides the designers with every conceivable opportunity to customize the device, removing the strongest argument for soft IP.

The following are some basic coding guidelines and conventions that will make any RTL code reusable and easily scalable and understandable.

• Rule - Develop a naming convention for the design, document it and use it consistently throughout the design.
• Architecture Naming Conventions
• Include Headers in Source Files
• Use Comments
• Keep Command on Separate Lines
• Indentation
• Do Not Use HDL Reserved Words
• Port Ordering
• Port Maps and Generic Maps
• VHDL Entity, Architecture, and Configuration Sections
• Use Only IEEE Standard Types
• Avoid Internally generated Resets
• Avoid Internally Generated Clocks
• Coding for Synthesis
• Avoid Latches
• Specify Complete Sensitivity Lists
• Case Statements versus if-then-else Statements
• Coding State Machines

These are only some of the rules and guidelines topics that we think are the most essential in creating reusable RTL codes.

The case study we will use consists of a design for a PCMCIA card that requires a CardBUS interface in the application. The CardBUS standard consists of the merger of two standards:

1)PCMCIA 16 bit PC Card and

2) Signal bus interface based upon PCI.

In this case, the designer needed to design a PCMCIA card to interface to a video camera with a laptop computer. The basic design blocks needed were a PCI interface, memory controller, state machines, memory block, miscellaneous glue logic and a proprietary bus interface. The designer had already designed the source code for the proprietary interface and was looking at how he could leverage that work that all ready had been done. The biggest issue was to develop a method of design that would allow them to implement the design at the lowest cost and spend the least amount of time and human engineering resource possible. Therefore, the solution to these needs was to reuse designs and to create reusable designs. This was important because this would be the first of a series of products that would be based on some of the basic building blocks with slight modifications or customization. Because they were to be similar they did not want to re-invent the wheel again, and design reuse was of the utmost importance. Various options were considered: 1) ASIC design, 2) Big FPGA, 3) Standard product with FPGA, 4) ESP solution

ASIC design — The volume was only going to be 5K to 10K units. NRE costs would be very high and the lifetime of the product would have to be very long for the product to be profitable. Design time would take up very long design cycles, designing everything from the ground up except for the proprietary bus, the use of IPs is an option but integrating different vendor’s IPs and putting together soft, hard and firm IPs together is not an easy task.

Once the design is verified it would be hard to leverage this design in order to migrate to another design.

Big FPGA — This option would require an expensive part, purchasing soft macros and integrating the needed parts could lower the design times. The problem is that it is hard to find compatible soft macros with the technology used, hence, timing issues would be very complicated to solve. In addition, integrating different vendors soft IPs could be a major hazard. Another issue about big FPGAs is that if they were SRAM based, then it would require an external ROM or EPROM to initialize it. This process is not only insecure but could also create timing problems.

Standard product — This option looks pretty good, but would require using fast expensive FPGA on the side, this would increase the size of the board, since the design is for a PCMCIA card, minimizing the size of the design is a very important issue. And like we mentioned before, it would also have the same issues as the previous option regarding to soft IP issues.

ESP solution — This solution seemed to be almost ideal. The ESP already had a PCI core embedded in the chip, which would require some customization. It is a single chip solution, hence saving a lot of board space. And the QuickPCI reference design kit has a SDRAM soft macro created by the design engineers at Quicklogic, so it was a matter of using that soft macro and creating some reusable blocks around it.

An ESP-based PCI solution provides much higher performance than today’s fastest solutions. An ESP PCI initiator/target controller core with a 75K gate FPGA including 12.7 Kbits of 5 nanosecond SRAM provides zero wait states since the ESP and FGPA are linked with higher than 100 MHz interconnects. It is also the lowest cost configuration because the controller is designed at the silicon level for the most efficient possible implementation. Design time is minimized because the system designer doesn't have to be concerned with silicon issues.

An important distinguishing feature of the new 66 MHz/64-bit PCI controller is that it is the first PCI-core designed from the ground up to attach to an FPGA. The designers incorporated all of the best features from existing cores and designed these features with the assumption that an FPGA is attached. That’s why the new core contains 360-plus interconnects — far more than has ever been provided by a PCI core. These interconnects provide three complete 64-bit buses plus all required controlling signals. This arrangement provides the designer with an unprecedented array of options.

The Quicklogic QuickPCI allows different application alternatives. One viable alternative is to route some embedded memory space on the FPGA to the PCI controller over one bus and use that to control the other two buses — one running from the FGPA to the PCI core and the other in the opposite direction. This arrangement provides order of magnitude increases in throughput compared to the fastest existing PCI controller designs. As a result, it provides enormous benefits to data communications, networking and video applications that can make use of this bandwidth. This approach also provides substantial reductions in cost and board space because it integrates functions that today require three or four discrete devices — the PCI controller, FIFO, FPGA and glue logic — into a single IC. Separate 64-bit buses could also be routed from the FPGA to different peripherals. An embedded controller could even be located on the opposite side of the FPGA.

This case study could be the base to migrate to a PC board version of the PCMCIA card, to upgrade from 32-bit to 64-bit, from 33MHz to 66MHz or 75MHz, without having to re-design the whole board. The design engineer in charge of this migration does not need to be the same person that created this design, and can still change the design with the least amount of time and cost.

In general, we can say that developers who do not follow some type of methodologies that would allow them to take advantage of reuse would not be able to keep up with the market needs. At the same time designers that choose wisely the best solution would get ahead of the competition.

Applications that are fundamentally based or related to basic previously designed building blocks are very common. Therefore, maximizing design reuse is a very important part of the design process. If we create designs with reuse in mind, we can lower costs and development time.

We were able to see that a design migration using ESP devices combined with soft macros is relatively simple. It gives the designer the possibility of creating products using short design cycles, and overall improving timing, performance and cost issues.

As engineers, our focus should be in creating new ideas, making these ideas a reality. We should not waste out time in re-creating parts that are already available to us.

Quicklogic’s ESP products are a revolution in the market because it gives the designer the opportunity to design new products, without having to worry about silicon issues, standard parts, etc.