Abstract

This paper defines the relationship between fault coverage and product quality at the device and printed circuit board assembly (PCBA)/multi-chip module (MCM)/system levels for system-on-chip (SoC) designs. It explores the design for test (DFT) characteristics that contribute to -- and detract from -- fault coverage improvements using chip-level scan synthesis and automatic test pattern generation (ATPG). The paper concludes with a discussion of how to validate the fault coverage of a particular design to insure that product quality requirements are met.

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