The demand for digital systems designers to create their product with more functionality, greater integration, in less time and at lower cost has never been greater. Such conditions, combined with advances in device technology, have led to an era where entire systems can be implemented on a single chip. The mere existence of these million and multimillion gate devices does not mean that creating system-on-a-chip (SOC) designs is easy, however. SOC design presents its own set of challenges to the industry that must be met by advances in several areas. First, system-level designs demand system-level device features, requiring device manufacturers to incorporate new elements into their components. Also, in the area of design development, better methods of design creation are necessary to ensure that a productivity gap does not arise between rapidly increasing device sizes and the ability of design teams to fill them. Advances in the area of intellectual property (IP) deployment and application will be particularly useful here.

EDA tools must become better integrated to allow designers to work seamlessly while taking advantage of competitive product offerings. Expanded design size also demands that verification will become more complex and critical to the overall design flow, and new verification tools must be developed to address this. Finally, changing and evolving standards as well as greater requirements for product modification and configurability will demand that the hardware implementation be flexible enough to accept these changes without slowing the overall design cycle. Advances in the programmable logic industry in all of these areas combined with the traditional strengths of these devices means that they are will positioned to meet many SOC design needs.

Today, beyond simply being larger, faster versions of their predecessors, PLDs incorporate structures that allow greater integration of design elements beyond simple logical gates. The most common of these is memory; most large-scale PLDs incorporate flexible memory structures which can be adjusted to meet many requirements. These on-board memories generally offer better speed than using external memory, and some even have dedicated circuitry for implementing specialized memory functions such as high-speed content-addressable memory or CAM, which has wide application in the communications field.

As more functions are integrated into devices that were previously individual components on the board, the number of different clock domains is likely to increase. As on a board, the clock signals for these domains may be related to each other, perhaps divided, multiplied or shifted versions of another clock. The most advanced PLDs today include some form of clock management, such as phase-locked loops (PLLs) and delay-locked loops (DLLs). The most advanced of these clock management schemes allow for high levels of control over clock generation and control. For example, clocks can be multiplied and divided using a wide range of multiplicands or divisors; low-skew clock signals can be generated for external use; individual clock signals can be phase shifted or delayed in increments as fine as half a nanosecond. The ability to generate high-speed clocks also aids in another area of SOC interest: support for high-speed I/O standards.

Several I/O standards have evolved to support low-voltage systems and higher data transfer rates. In order to accommodate the widest array of potential SOC applications, several of today’s PLDs offer support for these standards, including LVTTL. LVCMOS, 2.5-V, 1.8-V, GTL+, SSTL-2, SSTL-3, AGP, CTT, and LVDS. LVDS is of particular usefulness in the communications industry, as it supports high-performance, low-power data transfers. At its highest speeds (such as the 622 Mbps achieved in SONET OC-12 applications), LVDS requires on-board clock management circuitry to divide or multiply the incoming or outgoing LVDS clock signal by a factor of 8, respectively.

Figure 1 shows the dedicated LVDS circuitry in a programmable logic device. For 622 Mbps operation, serial data is clocked into the LVDS circuitry. The built-in PLL performs an 8X multiplication on the LVDS2 clock to clock the serial-to-parallel converter. Source: Altera Corporation.

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EDA tools for SOC design must do more than simply convert design descriptions into netlists for hardware implementation, they must allow for the new methods of design creation and verification. SOC designs are increasingly being developed by teams of designers rather than a single individual. Accordingly, their EDA tools need support for schemes such as the workgroup-computing model found in large-scale software development. In this model, a single EDA tool maintains the design database and allows individual team members to "check out" portions of it as they require. The tool monitors the read and write privileges for each of the design subsections, ensuring that a section does not get written over accidentally.

In the workgroup computing example shown in Figure 2, the designer working on design section D has full read and write capability, but of the two designers looking at design section A, only one has write capability. This design management scheme allows the individual designers to pursue their own modifications and compilations while advancing the project as a whole. Source: Altera Corporation.

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One of the realities of system-level design is that the engineers undertaking these projects will use a variety of EDA tools from different vendors. As long as there are competing EDA solutions, there will be reasons to use differing sets of tools, perhaps even a different set for each project. Accordingly, the onus is upon EDA tools vendors to work together to ensure that their tools interact with one another seamlessly and can pass data between each other with minimal user intervention.

One way of achieving this seamless interoperability between tools is to make the software application programming interfaces (APIs) available to other EDA vendors, allowing their tools to invoke and run the tool with an open API. With an open API and cooperation between EDA vendors, design constraints, netlists, timing information, etc. can be passed between tools without forcing the user to generate and transfer this information. Another benefit of the open API is the ability to locate the source of error messages within the appropriate tool. Without this functionality, it is often difficult to locate the sources of errors if the design has passed through one or more tools, resulting in some translation and the loss of individual node names. Some programmable logic tools feature this open API, allowing users to utilize EDA tools from their vendors of choice without suffering the difficulties of a non-integrated development environment.

The ability to maintain and increase levels of productivity in the era of SOC design requires more than advancements in EDA tools; it is also founded on design reuse and integration of IP, both from internal and external sources. Rapidly advancing technologies in nearly all areas of system-level design makes it difficult for any given design group to maintain all the expertise required to develop their product. This phenomenon, combined with growing time-to-market pressures, is forcing companies to focus on their core design competencies, while relying on other sources for expertise outside of their realm. On the surface, this trend appears as a rise in the use of IP and specialized design consultants. In the long run, however, the full potential of IP use is only realized when infrastructure is in place to allow potential users to evaluate several competitive IP offerings from different providers.

Figure 3 shows one of the configuration screens for 32-bit processor IP optimized for programmable logic. Users can determine their desired processor characteristics using these and other configuration screens. Partnerships between PLD vendors and processor IP developers ensure that PLD users get architecture-optimized processor cores for their designs. Source: Tensilica, Inc.

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IP for programmable logic is a relatively new wrinkle in the IP landscape. Although IP for ASICs is generally more familiar to system designers, IP that is destined for use in PLDs should be optimized to take advantage of the specific architectural structures found in the target device. Luckily, PLD vendors are creating many IP products of their own, and are working with IP providers to produce PLD-optimized version of their products. The major PLD vendors now offer a wide portfolio of IP products, ranging from DSP functions to error detection/correction, cryptography, and 32-bit processors. Perhaps most importantly, evaluation programs are in place to allow potential IP users to investigate and verify many of these IP cores in their designs free of charge before committing them to silicon, resulting in very little risk for the designer.

As design complexities rise, traditional methods of design verification like simulation will need to be supplemented by other techniques and tools, because the full range of real-world stimulus for designs in this realm cannot be simulated in any reasonable amount of time. Also, the sheer increased size of designs will demand that new tools be created to scrutinize the internal operation of the programmed device, especially with the increased use of third-party IP which requires internal probing to verify operation separate from the rest of the design. Finally, due to advances in packaging technologies, new methods will have to be developed to facilitate hardware verification of increasingly small and dense packages like BGAs.

A new technology, SignalTap, has been developed to address these needs. SignalTap allows a designer to inspect a PLD’s internal signals while it is in operation. These signals can be viewed as waveforms on the user’s workstation linked to the PC board via a download cable, or via traditional board analysis equipment. With SignalTap, a user can study the operation of the design in a fashion similar to using a logic analyzer; initialization, triggering (internal or external) and display conditions can be set, and any internal signal can be accessed. The user’s analysis parameters are compiled into an embedded logic analyzer (called the SignalTap megafunction) and programmed into the device along with the rest of the design information.

Programmable logic offers a set of well-known advantages to system designers, including high levels of flexibility and short development times, allowing designers to quickly create working hardware and bring their products to fruition. However, increases in device size, advances in system-level design features, improvements in PLD-related EDA tools, and the rising number of IP solutions available in a broad range of design areas are rapidly making programmable logic the integration platform of choice. This trend indicates that the million- and multimillion-gate device design of the future will not be merely a system on a chip, but rather a system on a programmable chip.

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