The Internet revolution is dramatically changing our lives today. The amount of packet traffic continues to accelerate and the packet processing function is becoming the key product differentiation for switching systems. Network processors address the flexibility required to address the changes in communications protocols and standards. Today’s network processors incorporate a multi-threaded/multi-processor architecture that allows users to implement packet-processing functions in software code. Some vendors incorporate several small RISC engines that are multi-threaded to process the packets in parallel. The architectures of the network processors differ from one vendor to another, but most incorporate a multi-processor approach in which the user programs the network processor via software code. Some vendors provide software development support using a high-level language such as C and C++, but many network processor vendors currently support a lower-level assembly-type language. The value proposition from the network processor vendors is the flexibility the network processors provide via the software approach and the potential time-to-market advantages compared to the traditional custom ASIC approach. To date, several vendors have introduced a number of off-the-shelf network processors to meet the needs of communications systems designers.

Programmable logic-based packet processing functions offer many of the same flexibility and time-to-market benefits of off-the-shelf network processors. Further, programmable logic can provide better performance by utilizing dedicated hardware for specific packet processing functions. Today’s programmable logic devices also offer features that are geared towards packet processing such as CAM, LVDS, and RISC processor capability. Finally, PLD users can also take advantage of a growing amount of communications-oriented IP to aid in shortening their design times. It is predicted that there will be increasing market consolidation of vendors who supply network processor functionality, but the concept and the potential application for network processors will continue to grow. For those designers who need the maximum amount of flexibility and performance combined with rapid prototyping cycles, programmable logic will be the solution of choice.

One method of effectively performing packet processing involves using programmable logic devices (PLDs). Programmable logic offers many of the same flexibility and time-to-market features that make network processors attractive when compared to custom ASICs. Further, programmable logic can provide better performance and potentially greater levels of integration than most off-the-shelf devices. Also, from a resource utilization perspective, programmable logic usage is much more efficient as there are no wasted resources/unused instructions, nor are there any functions that are not intended or well-suited for the designer’s specific task at hand. Finally, the recent availability of 32-bit RISC soft cores for programmable logic adds another level of capability to these devices, affording users greater usability and the option to rapidly develop custom multiprocessor designs.

The better performance provided by programmable logic arises from the dedicated hardware that a designer can devote to a specific function in a PLD that might otherwise be performed sequentially in software in a network processor. For the same operation, hardware implementation will always be faster than software implementation. Similarly, in the area of digital signal processing, many PLD vendors have shown that higher performance is achievable with PLDs for many functions when compared to the same function being performed by a DSP processor. Today, many communications system vendors developing high-end switches and routers have implemented packet processing functions with PLDs that are running at OC-48 wire speeds. Here, PLDs are used in all of the key datapath functions, including search engines, packet classification, buffer/queue management, QoS functions, and fabric interface logic. Additionally, several packet processing-related intellectual property (IP) functions that are optimized for programmable logic are available, including media access control (MAC), packet classification, CRC generation, encryption/decryption, and compression.

Some of the latest programmable logic devices incorporate dedicated content-addressable memory (CAM). CAM is useful for high-speed searches and thus has many applications in communications functions. For example, CAM can be used in search engines and QoS functions such as policy management as well as label look up in Multi-Protocol Label-Switching (MPLS). Figure 1 shows CAM usage in policy management, in which a combination of CAM and RAM is used to determine the QoS permissions for a given packet.

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Another application of CAM is in the look up of labels in MPLS. MPLS uses labels to simplify routing within a network. Labels are attached to packets in ingress edge routers when they enter the network. Then, the labels are used and switched in core routers as the packets travel through the network. Finally, egress edge routers remove the labels when the packets leave the network. Figure 2 shows how a combination of CAM and RAM in each router in an MPLS network can be used to look up and switch labels. The ingress edge routers incorporate CAM that holds IP addresses in its data space and addresses to an associated RAM in its address space. The IP addresses correspond to the packet’s destination. The IP address of the incoming packet’s destination is looked up in the CAM, and a RAM address is output. This RAM address is looked up in an associated RAM and the corresponding label is found in the RAM’s data space. The label, which indicates the packet’s next destination in the network, is appended to the packet, which is then sent on. The CAMs in the core routers serve a similar purpose, except that instead of housing IP addresses in their data space, they have labels. In the egress routers, the RAMs hold IP addresses corresponding to the packets’ next hop.

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The greater integration that large-scale PLDs deliver leads to higher performance by eliminating on-chip/off-chip delays, but signals must ultimately come on and off the PLD itself. Support for high-speed I/O standards ensures that on-chip/off-chip delays are minimized, which is particularly important for the interface to the switch fabric. Some PLDs include support for the Low-Voltage Differential Swing (LVDS) I/O standard at speeds as highs as 840MB/s. The on-board phase-locked loops included in many advanced PLDs also aids in maintaining speeds by generating multiplied clocks for use both on-chip and off-chip, allowing different functional blocks to be clocked at speeds which are ideal for their operation.

The combination of flexibility and performance promised by network processors is a step in the right direction towards the meeting the heavy demands of the communications market. However, the market is not static, and the need for more bandwidth is increasing. The transmission speeds in the WAN backbone has been shifting from OC-12 to OC-48 and now to OC-192 and beyond. With Dense Wave-Division Multiplexing (DWDM) technology, multiple channels of OC-48 and 192 signals can be transmitted on a single fiber optics line. Even in the Metropolitan Area Network market, with the commercial shipments of 10 Gigabit Ethernet expected in 2001 to 2002 timeframe, the transmission bandwidth is increasing exponentially. With this rapid increase in bandwidth speeds, the switching systems must now be able to process packets and forward traffic at these high-speed wire rates.

Based on these market trends and the issue of differentiating the end system, several questions arise regarding the pure software and multi-processor architecture approached utilized in network processors to do packet-processing functions. First, it is unclear if this approach will be able to meet the foreseeable need to process packets at OC-48 and OC-192 wire speeds. Also, the level of system differentiation provided by a pure software approach may not be sufficiently broad enough for end products to compete effectively in the market. If the designers have some value to add in the form of hardware implementation at the packet processing level, then they would be hard pressed to incorporate it into a network processor-based product. Another question arises about the portability of software from one generation of network processor to another or from one vendor’s network processor to another. Currently, an industry consortium called the CPIX Forum is at work defining standards in this area, but their work has yet to be finalized, and even after that, the various vendors still must adopt it. Until then, software development for many of the network processors remains a task involving non-portable code.

The Internet revolution has dramatically changed the traffic pattern in today’s communications networks. Today, there is more data traffic than voice traffic in our networks. The communications network is rapidly evolving from a circuit-switched network to a packet-switched one with the rapid convergence in voice, video, and data. With the significant growth in the packet-switched networks, it is becoming increasing important to provide higher performance, feature-rich, high Quality of Service (QoS) packet processing functions. From LAN switches to core routers in the Internet backbone, whenever you handle a packet, you need to perform packet processing before you transmit the packet from the egress port. Traditionally, the packet processing function was performed either by an ASIC or a CPU. The ASIC provided the maximum performance since the packet processing was implemented in hardware, but lacked the flexibility and "time-to-market". Microprocessors or CPUs on the other hand, provided flexibility based on the software approach, but lacked performance. To provide a combination of hardwired performance and programmable flexibility optimized for packet processing, the concept of the network processor was introduced.

A typical network processor discussed in the market today performs many of the packet processing functions, including framing, classification, modification, searching, encryption, and queuing. Differences in the implementation of these packet processing functions are often the keys to differentiating the offerings of the network processor vendors and the products in which they are used. For value-added mid-to-higher ended switching/routing systems, the packet processing function is the core competence of the system vendor.

Today’s programmable logic solutions offer the flexibility, performance, and the rich feature set to develop effective packet processing functions. The availability of RISC cores adds hardware reconfigurable capabilities that opens new opportunities for programmable logic devices in packet processing applications. Programmable logic technology continues to evolve in a rapid pace and the capability of the devices continues to increase exponentially.