Programmable Logic and High-Speed Serial I/Os
Murray Disman (mdisman@ix.netcom.com)
Editor, Programmable Logic Knowledge Center
eChips

We are at the start of an interesting and very important change in the way parts are interconnected on a PC board, within an equipment chassis, and between equipment boxes. This is the transition from parallel-bus architectures, such as PCI and VME, to differential high-speed, serial point-to-point connections in a switched fabric architecture. There are basically two factors driving this transition: limitations of the parallel-bus architecture and the progress made in the design and implementation of multi-Gb/s CMOS high-speed serial transceivers.

Shared-bus throughputs have not been able to keep up with the rate at which CPU clock speeds are increasing. Attempts to increase the bandwidth of a shared bus by increasing the clock speed and/or increasing the width of the bus are reaching their limits. PCI-X, for example, can handle only one slot when running at its top speed of 133MHz. The new standard supports only two slots when the clock speed is dropped to 100MHz.

Increasing the width of the bus seems like a simple way to increase bandwidth. However, the amount of board space and the number of board layers and package pins required have made this an expensive alternative. The relatively slow adoption of 66MHz/64-bit PCI compared with that of the 32-bit options reflects these difficulties. Other problems associated with the wide-bus approach are EMI effects and the difficulty of keeping the signals aligned over even modest distances.

High-speed serial point-to-point connection techniques have been used in electronic equipment for some time. One of the most prevalent examples is the use of LVDS for backplane interconnections. Another is the Fibre Channel standard, which was originally defined for industrial control systems but has recently become popular for interconnecting disk arrays and servers.

What has recently changed is the ability to implement the multi-Gb/s transceivers in CMOS circuitry. In the not too recent past, it was necessary to use bipolar or GaAs ICs to drive the copper or optical serial links. CMOS high-speed serial transceivers are now being implemented in ASICs, as standalone products (ASSPs), and embedded in FPGAs.

Most of the FPGA producers plan to introduce devices that combine FPGAs and dedicated embedded multi-Gb/s I/Os during 2001. Altera, Lucent, and QuickLogic are already shipping devices with embedded circuitry to implement dedicated high-speed differential I/Os. Xilinx has been able to incorporate such a capability in its general purpose Virtex I/Os.

Altera was the first to adopt the embedded approach in its APEX 20KE series. The larger devices in this family contain embedded LVDS circuitry that can attain speeds of 840Mb/s. The maximum speed of Xilinx's general purpose I/Os in the Virtex-E family is 622Mb/s, when configured for LVDS operation.

Lucent and QuickLogic have opted to produce special devices with high-speed serial I/Os, rather than to incorporate these in their general purpose FPGAs. QuickLogic can claim the highest I/O speeds for devices that are now available. Its QuickSD series contains up to eight dedicated 1Gb/s LVDS transceivers. Lucent is producing the ORT4622 with four embedded 622Mb/s LVDS I/Os and the ORT8850H with eight embedded 850Mb/s transceivers.

Cypress, with its new Delta 39K series of high density CPLDs, Lucent, QuickLogic, and Xilinx have all announced plans for producing parts with dedicated I/Os with differential transceivers that can operate at speeds exceeding 1Gb/s. It is interesting that Altera, the first to embed circuitry for LVDS I/Os, has not divulged plans to extend these above the 1Gb/s mark.

QuickLogic and Xilinx have licensed the SkyRail core from Conexant. Xilinx intends to provide the 3.125Gb/s I/Os in its 0.13-micron Virtex-II devices and to deliver samples during 1Q2001. QuickLogic will incorporate the cores in its next-generation QuickSD family and expects to provide an aggregate data speed of up to 37.5Gb/s. The company has not yet disclosed a schedule for the release of the new family.

These cores are based on Conexant's SkyRail SRP3100, which is shown in Exhibit 1 and is a CMOS-based standard product with 3.125Gb/s transceivers. The company offers the part as an ASSP and as an IP core.

Exhibit 1 - Conexant's SkyRail Link SRP3100

Source: Conexant

Cypress and Lucent intend to use internally developed technology to deliver PLDs with dedicated multi-Gb/s I/Os. Lucent's ORT82G5, which is scheduled for March 2001 availability, will contain eight channels, each of which can operate at speeds of 1.25, 2.5, or 3.125Gb/s.

Cypress has recently announced that it will port its HOTLink transceiver technology to its Delta 39K parts and start sample delivery during 1Q2001. The company recently introduced the CY7B926V, a standalone product that integrates a 2.5Gb/s transmitter, receiver, clock and data recovery circuit, SERDES, and 8B/10B encoder-decoder. The new series of high-density CPLDs with integrated HOTLink transceivers is being called the Programmable Serial Interface (PSI) family. The family contains a number of parts with up to two 2.5Gb/s ports or up to eight ports that can operate from 0.2 to 1.5Gb/s.

Xilinx seems to have the most extensive program aimed at integrating high-speed serial transceivers with its Virtex-II devices. The company acquired RocketChips primarily to bolster Xilinx's capability in the CMOS mixed-signal and serial-transceiver design areas. RocketChips has developed high-speed serial cores for Gigabit Ethernet, Fibre Channel, IEEE-1394 (Firewire), and other serial link transceiver applications.

Xilinx has also announced that it will be collaborating with Motorola on product development involving the emerging RapidIO interconnect architecture. Motorola plans to use Xilinx FPGAs that incorporate RapidIO intellectual property, or cores, to validate future Motorola products with RapidIO technology. Xilinx will use bus-functional models developed by Motorola to validate the Xilinx RapidIO cores targeted for its Virtex-II FPGAs.

Exhibit 2 shows a number of the high-bandwidth I/O standards that exist or are being developed, and Exhibit 3 shows how these and other standards are being applied to satisfy interconnection requirements in the different parts of a system.

Exhibit 2 – High-Bandwidth I/O Standards

Source: Xilinx

Exhibit 3 – System Bandwidth Requirements

Source: Xilinx

The three standards receiving the most attention today are Infiniband, 10Gb Ethernet, and RapidIO. The InfiniBand Trade Association was founded in August 1999 by Compaq, Dell, Hewlett-Packard, IBM, Intel, Microsoft, and Sun Microsystems. It has more than 180 members working to create a specification for a channel-based switched-fabric server I/O architecture that provides for a scalable performance range of 500MB/s to 6GB/s per link. The 1.0 version of the specification was released in October 2000.

The RapidIO architecture was developed by Motorola and Mercury Computer Systems, Inc. and announced in February. It is now offered as an open standard through the RapidIO Trade Association.

These standards are receiving wide industry support, but are aimed at very different system applications. RapidIO is primarily for in-box interconnections of up to 30 inches in length, while Infiniband will be used for connecting equipment boxes separated by as much as 30 meters. The RapidIO work is being driven by the producers of networking and telecom equipment. Infiniband is being developed by the computer, server, and disk-array manufacturers, and 10Gb Ethernet is being developed by the producers of LAN and MAN systems.

RapidIO is designed to provide an aggregate bandwidth of 10Gb/s using an 8-bit-wide bus. The port width can scale to 16 bits, and the LVDS signaling technology has the capability of scaling to multi-Gb/s speeds. Exhibit 4 shows how RapidIO could be used to interconnect a variety of processors and memory and bridges to existing systems and networks. Exhibit 5 shows RapidIO in a backplane application.

Exhibit 4 – The RapidIO Interconnection Scheme

Source: RapidIO Trade Assoc.

Exhibit 5 – RapidIO in a Backplane Application

Source: RapidIO Trade Assoc.

Even though Infiniband and 10Gb/s Ethernet will be important protocols, RapidIO and RapidIO-like approaches will be more broadly used as RapidIO is oriented toward chip-to-chip and backplane interconnections. There will be many more RapidIO connections in a system than either Infiniband or 10Gb/s Ethernet links. RapidIO is designed to work with PCI but, in many instances, it will replace this popular bus standard.

Reaching the 1.25Gb/s RapidIO speed would be nice but not necessary. LVDS is already being used for many backplane designs. Companies are developing their own RapidIO-like designs and running these at speeds compatible with cost requirements. Clearly, the higher speeds are desirable and we can expect a steady upward migration in speed as new parts are introduced and costs decrease. Xilinx, for one, expects serial backplane architectures to grow from 5% to 100% of network system architectures over the next few years.

One of the more important factors behind the current boom in FPGAs sales has been the board-level integration role taken on by these devices. The ability to program the I/Os to meet a variety of signaling standards in the Altera APEX, Cypress Delta 39K, QuickLogic Eclipse, and Xilinx Virtex families has proven to be a real cost-saver by eliminating the need for separate translators.

The new high-speed serial ports will require embedded circuitry leading to dedicated I/Os, losing some of the flexibility of the programmable I/Os. In addition, there often is the need to embed the SERDES (serializer/deserializer) and possibly an encoder/decoder along with the transceiver. To benefit from this trend, some clever design work and astute market assessments will be required by the FPGA suppliers.

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