Mark Rootz

Applications Manager, STMicroelectronics PSM Division

As process technologies get ever smaller, an increasing amount of system functionality can be integrated on a single chip. In some instances, this has led to the implementation of entire systems-on-chips or SoCs. Most SoCs are custom ICs, but a variety of off-the-shelf devices are available that offer near system-level integration, as well as programmability. There are two basic types of off the shelf programmable system-level integrated circuits: the so-called programmable system-on-a-chip and the programmable system memory (PSM).

Programmable SoCs integrate a processor, programmable logic and SRAM. In the last year, several IC vendors have introduced devices with this architecture. All programmable SoCs introduced so far are SRAM-based and, therefore, also require an external EEPROM or flash memory to store the MCU code and FPGA configuration data. Because of this, they are not really systems-on-chips. They provide an attractive two-chip solution for designs that need a fair amount of programmable logic, require a small amount of code storage, have limited or no data logging storage, and, in some cases, require the throughput provided by a 32-bit processor.

The second type of programmable system-level integrated IC, the programmable system memory, integrates a modest amount of programmable logic with fairly high density flash memory, SRAM and a programmable microcontroller interface. These devices include everything, except the system microcontroller, so they also provide a two-chip solution with the second chip being any of hundreds of 8- or 16-bit microcontrollers. The best known vendor of programmable system memories is STMircoelectronics.

The programmable system memory is preferable for designs where the programmable logic requirement is minimal, the firmware storage requirement is large, SRAM requirement is large, and/or there are substantial data logging requirements. Such applications include medical monitoring equipment, networked manufacturing control and data collection, point-of-sale products (bar code readers, vending control, etc), GPS devices, graphics controllers, and other embedded systems.

Deciding which highly integrated two-chip solution to use depends on how the application’s requirements mesh with the architecture of the device.

Programmable Logic - Programmable SoCs have fairly large programmable logic arrays with 40,000 or more gates. In the lower end devices the logic is used to implement MCU peripherals, such as CAN, I2C, and serial ports. The higher performance, more complex devices that will be offered by other vendors eventually will have as many as a million system gates of programmable logic. These devices and will be able to implement complex intellectual property cores, such as speech codecs, MPEG 4 and so forth. However, no matter how many system gates they have, for the foreseeable future, these programmable SoCs will require a second IC in the form of an external non-volatile memory to load the FPGA configuration and processor code.

Programmable system memories, on the other hand, have between 3,000 and 5,000 gates of programmable logic. This logic is used to mate with the interface to the microcontroller, to implement such peripherals as processor mail boxes, keypad scanners, timers, counters, interrupt controllers, and shift registers. Programmable system memory devices do not have sufficient logic to implement more complex peripherals, although frequently it is possible to get the required peripherals on the MCU core the designer selects for this solution.

On-Chip Memory - The memory on programmable SoCs is limited to the available on-chip SRAM, typically about 32 KBytes in devices that are currently in production. The SRAM on these devices is used for code execution as well as date storage, so they may not be the best choice for designs that have very large MCU code or extensive data storage needs.

As the name implies, programmable system memories have lots of memory, up to one megabyte of flash memory, and as much as 32 KBytes of SRAM, plus a second 32 KByte flash memory array that enables in-application programming (IAP). Since flash memories may not be updated while code is being read from them. A second array is always required for IAP. The large flash memory of programmable system memories provide plenty of storage for large programs written in a high-level language (C, C++), real-time operating systems (RTOSs) and for the storage of large data logs. This ability to log large amounts of data is important for any type of monitoring system, particularly those in remote locations. In this type of two-chip solution, the MCU executes from the flash on the device. Since flash memory is fairly slow, programmable system memories are not usually suitable for use with very fast 32-bit processors. However, they offer fast enough access times to support virtually any 8- or 16-bit controller. Executing from the flash memory keeps the SRAM free for the storage stacks and to buffer data to and from communication channels.

The Microcontroller - Programmable SoCs offer a range of on-chip processors from the humble, but ever so popular, 8051, to ultra high performance processors. At this point, programmable system memories do not have an on-chip microcontroller at all. Having the processor on-chip has the advantage of increasing MCU performance. However, an on-chip MCU may not always be an advantage, particularly if the microcontroller that is preferred for the application is not available on a programmable SoC. The designer is necessarily locked into the microcontroller(s) offered by the programmable SoC vendors. If there is a lot of legacy code written for a particular MCU that is not supported by a vendor of programmable SoCs, the designer will have to learn a new instruction set and re-write the code for the MCU that is on the programmable SoC. When this is the case, the performance improvement to be gained from using a programmable SoC should definitely outweigh the cost of re-writing the code.

A programmable system memory has a built-in interface to hundreds of 8- and 16-bit microcontrollers from ST, and others, so the designer has nearly perfect freedom regarding the type of controller to use and existing code can be re-used. The MCU interface can be configured in less than a minute using software. In addition, since virtually any MCU derivative can be specified with a programmable system memory, it is likely that peripherals that might be implemented in programmable logic on a SoC can be acquired much less expensively on the MCU.

System Cost - Programmable SoCs can be fairly expensive. Low-end devices cost (e.g. 8-bit MCU) about $9 in volume. The price for the high performance 32-bit varieties are expected to be in the $45 to $50 range in production quantities. The external EEPROM for these devices will cost an additional $2 to $3, depending on the size of the FPGA and its configuration file. The least expensive programmable SoC solution can be expected to cost at least $11.

Programmable system memories tend to be less expensive, starting at as little as $3.50 each in volume and going up to as much as $7.50 for devices with the highest density memories. The core microcontroller will usually cost $1 or less, resulting in a total solution that costs between $4.50 and $8.50, about half the cost of the least expensive programmable SoC solution. Thus programmable system memories may be preferable in cost-sensitive designs that do not need the higher performance offered by the programmable SoC.

Design Flow - A final consideration in selecting a two-chip embedded solution is the design flow. With a programmable system memory, the designer uses standard compilers, debuggers and in-circuit emulators (ICEs) for code design as would be the case when doing a conventional design with discrete components. The microcontroller core remains an independent device that is supported by all the same RTOSs and third party development tools as always. The logic part of the design in a programmable system memory is done using a combination of point-and-click menus in the support tools that automatically generate the hardware description language (HDL) for the MCU configuration and memory paging and decoding, plus pre-defined HDL templates for logic to be implemented in the programmable logic.

Among programmable SoCs, there are a number of choices. Some programmable SoCs provide design tools that allow the designer to simply drag and drop the peripherals to be implemented in the programmable logic - a pretty much fool proof method for designing peripherals. Other devices offer co-design and co-simulation tools that allow the FPGA design tools to be used within the same framework as the microcontroller debug software and allow the HDL description to be simulated concurrently with the MCU code. There is little information available on the design flow for higher-end programmable SoCs. Silicon is not yet available for these devices and the vendors have been pretty closed mouthed on the subject. At present, there is neither ICE nor RTOS support for programmable SoCs.

Conclusion - The number of highly integrated programmable ICs for embedded systems is rapidly expanding so designers have lots of solutions from which to choose. At the present time all of them will consist of two chips, either a core microcontroller or an external non-volatile memory. Which solution is the best one should be dictated by the memory, performance, and programmable logic requirements of the application.

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