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A Methodology for the Concurrent HW/SW Design of Programmable Systems-On-Chips Email: mmason@atmel.com Introduction - Programmable Systems-on-Chips Market research indicates that more than 400,000 new 8-bit embedded systems will be started in the next 12 months. Of these, about 25% include some programmable logic on the side to handle datapath operations or to create custom peripherals. Although using programmable logic in these discrete designs improves the functionality and flexibility of these systems, it also increases board size, power consumption, and manufacturing cost. Today these designs are done by two different types of designers: the embedded designer who writes the code for the processor; and the hardware designer who designs the FPGA logic and its interface to the processor. Final system level integration is a time consuming challenge, that requires a prototype board, waveform analyzers and In Circuit Emulators (ICE). Recently, several silicon vendors have introduced programmable systems-on-chips (SoCs) that integrate a processor, memory, peripherals and programmable logic on a single piece of silicon. Although some of these devices are targeted toward the FPGA designer who is in need of an on-FPGA processor, others, including Atmelıs FPSLICı family of Field Programmable System-Level ICs, are targeted toward the embedded system designers who need a high performance processor with some programmable logic for datapath logic, application acceleration or customized peripherals, plus a relatively large amount of memory for program and data storage. Programmable SoCs provide an exceptionally small footprint and low power embedded system solution. Click here to read the complete article (32k).
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