| Date |
Headline |
Author |
| 03/11/03 |
The Benefits of FPAA Technology for Implementing Analog Designs |
Suhel Dhanani, Anadigm |
| 07/16/02 |
Maximizing Embedded System Performance in the Era of Programmable Logic |
Altera Corp. |
| 04/22/02 | DSP Design Using a True Top-down Design Methodology | AccelChip |
| 01/21/02 | Design Security in Nonvolatile Flash and Antifuse FPGAs | Actel |
| 12/11/01 | A Methodology for the Concurrent HW/SW Design of Programmable Systems-On-Chips | Martin Mason |
| 10/24/01 | Implementing Control Logic in Today's "Multi-Voltage" Systems | Suhel Dhanani and Mr.Hiroyuki Yamashita |
| 08/28/01 | Programmable Logic Facilitates the Implementation of OFDM Based Systems | Tapan A. Mehta, Altera Corporation |
| 08/28/01 | FPGAs Driving Voice-Data Convergence | Amit Dhir, Xilinx Corporation |
| 07/10/01 | Implementing LED Drivers in Product-Term Based PLDs | Frederick Lo, Altera Corporation |
| 06/09/01 | Transition of Broadband Access Devices to Residential Gateways | Amit Dhir, Xilinx Corporation |
| 04/27/01 | Selecting the Right Two-Chip Solution for Embedded System Designs | Mark Rootz, Applications Manager, STMicroelectronics PSM Division |
| 03/27/01 | A Design Methodology for The Efficient Implementation of Complex DSP Algorithms in FPGAs | Johannes Steensma, Frontier Design |
| 02/23/01 | Using Product-Term Devices to Replace Discrete I/O Drivers | Jennifer Stephenson, Altera Corp. |
| 02/05/01 | A study of high-performance reconfigurable constant coefficient multiplier implementations | Philip James-Roxby and Brandon J. Blodget, Xilinx, Inc. |
| 12/29/00 | Programmable Logic and High-Speed Serial I/Os | Murray Disman, eChips |
| 11/30/00 | Support for Multiple I/0 Standards; Another Required Checkmark for Today's CPLDs | Suhel Dhanani, Altera Corp. |
| 11/12/00 | Guided Synthesis Using FPGA Express/FPGA Compiler II Block Level Incremental Synthesis | Karen Fidelak, Xilinx, Inc |
| 10/15/00 | Building Configurable Network Processors | Hiro Higuma and Martin S. Won, Altera Corporation |
| 09/18/00 | Using the Internet to Repair Hardware in the Field | Neil G. Jacobson, Xilinx, Inc. |
| 08/07/00 | Newest FPGAs Designed to Support 160 Gbps Buffered Communications Crossbar Switches | Peter Alfke, Xilinx, Inc. |
| 07/21/00 | Programmable Logic and the Challenges of System-on-a-Chip Design | Martin Won, Altera Corporation |
| 06/19/00 | Evolution of the Programmable Logic Industry | Murray Disman, ChipCenter's PLD Design Center |
| 06/05/00 | Processing Digital Signals With Programmable Logic Devices | Tony San, Altera Corporation |
| 05/15/00 | PCI to Gigabit Tx/Rx Chipset Controller | Brian Faith, QuickLogic |
| 05/01/00 | Using FPGAs to Build an MP3 Player | Robert Bielby, Xilinx, Inc. |
| 04/14/00 | Impact of DFT on Fault Coverage and Product Quality in SoC Designs | Jon Turino, SynTest Technologies, Inc. |
| 03/24/00 | New IP Evaluation Model Reduces Risk, Speeds FIR Filter Design Time for Communications Test Equipment | Charlie Evans and Jeff Fox |
| 03/10/00 | Maximizing Intellectual Property Reuse for PCI | Brian Faith and Mao T. Wang |
| 02/21/00 | An Open System Approach For Verilog and VHDL Debugging | Scott Sandler |
| 02/04/00 | Configurable Logic For Digital Communications | Chris Dick and Fred Harris |
| 01/17/00 | Seizing Control of the Design Process | Viewlogic Systems, Inc. |
| 01/05/00 | Evolving Verification Techniques in PLD Design | Suhel Dhanan |
| 12/23/99 | Re-configurable Logic Cores for SOC Devices | Mark Scheitrum |
| 12/07/99 | Solidification ý Static Functional Verification with Solidify | Graham Bell |
| 11/29/99 | New LVDS Capabilities Giving 422 and 485 a Run for the Money | Kevin Gingerich |
| 11/11/99 | The Future of System Design: Configurable Cores and CPLDs | Martin S. Won, Bernie Rosenthal |
| 10/28/99 | SEU Mitigation Techniques for Virtex FPGAs in Space Applications | Carl Carmichael, Earl Fuller, Phil Blain, Michael Caffrey |
| 10/06/99 | Block-Based Prototyping Methodology | Aptix Corporation |
| 09/22/99 | Demystifying FPGA to ASIC Conversion | Bob Kirk, CAD Research Manager, American Microsystems Inc. |
| 09/08/99 | Architectural Synthesis and Design Re-use | Marc Van Canneyt, Vice President of Business Development, Frontier Design, Inc. |
| 08/25/99 | Configurable Logic for Digital Signal Processing | Chris Dick, Bob Turney (Xilinx Inc.) and Ali M. Reza (University of Wisconsin) |
| 08/03/99 | Reconfigurable High Speed Arithmetic Functions in a Non-Volatile FPGA | By Rufino T. Olay III, QuickLogic Corp. |
| 07/26/99 | Development of Reusable Algorithms Based on C and C++ | By Doug Johnson, Frontier Design, Inc. |
| 07/09/99 | Incremental Synthesis and Place and Route using LeonardoSpectrum | By Tom Hill, Exemplar Logic |
| 06/30/99 | The 1999 Design Automation Conference | By Murray Disman |
| 06/14/99 | Increasing Importance of HDL Verification | By Gregor Siwinski, Aldec Inc. |
| 06/07/99 | FPGA-Based System Level Integration | By Joel Rosenberg, Atmel |
| 05/12/99 | Remote Field Updates Using FPGAs | By Tom Branca, Chris Stinson and Brant Soudan, Xilinx, Inc. |
| 04/29/99 | Improving Performance in Complex Programmable Logic Devices (CPLDs) with the FPGA Express Software | Phil Simpson, Altera Corporation |
| 04/13/99 | A Cost Effective Image Acquisition, Real-Time Processing and Display Architecture Using FPGA Technology | John Smith, Principal Engineer, VisiCom, and Sheldon Liebman, Industry Advisor |
| 04/06/99 | IP'99 Conference Report | Murray Disman, Editor EDTN PLD Design Center |
| 03/17/99 | Pipelined Design for CPLD Improves System Performance | Jimmy Gao, Lattice Semiconductor Corp. |
| 03/10/99 | Integrating Multiple CPLD Functions in an Actel SX Device | Lone Star Logic, Inc. |
| 02/24/99 | The Programmable Logic Proving Ground | Tom Troksa, Packet Engines (part of Alcatel), Steve Dabell, Packet Engines, and Martin S. Won, Altera Corp. |
| 01/20/99 | New FPGA Architectures Address Wide Gating Functions | Om Agrawal and Bill Harding, Vantis Corp. |
| 01/13/99 | Accelerating DTP with Reconfigurable Computing Engines | Donald MacVicar, The University of Glasgow and Satnam Singh, Xilinx Inc. |
| 12/16/98 | Optimal HDL Coding Styles for Programmable Logic Design | Suhel Dhanani, Altera Corporation |
| 12/16/98 | BoardScope: A Debug Tool for Reconfigurable Systems (.pdf formate) | Delon Levi and Steven A. Guccione, Xilinx, Inc. |
| 12/09/98 | Fibre Channel Multimedia Adapter With PCI Bus Interface Using ORCA FPGAs | Alan Cunningham, Lucent Technologies |
| 12/02/98 | PCI Bus Target Controller Implementation Using a Lattice ispLSI CPLD | Bertrand Leigh, Lattice Semiconductor |
| 11/11/98 | Automatic Hardware Synthesis for a Hybrid Reconfigurable CPU Featuring Philips CPLDs | Bernardo Kastrup, Philips Research Laboratories |
| 11/04/98 | Error Control Coding Functions in Programmable Logic | Tapan A. Mehta, Altera Corporation |
| 10/28/98 | FPGA Large Device Design Methodology | Tom Hill, Exemplar Logic |
| 10/21/98 | An Emerging Solution For Embedded System Design | Chris Balough, Triscend Corp. |
| 10/14/98 | Combining FPGA Cores To Extend The Performance Of DSP Designs | Paul Laity and Sabine Lam, Xilinx, Inc. |
| 10/07/98 | Meeting the Synthesis Challenge of Complex Programmable Devices at 100K gates and Beyond | Darron May, ALT Technologies |
| 09/23/98 | Implementing 155 Mbps ATM in High-Speed, High Density, FPGAs with On-Chip RAM | Joaquin Aviles of Cisco Systems Inc. & Brian Faith of QuickLogic Corp. |
| 09/16/98 | The Java API for Boundary-Scan | Neil Jacobsson, JTAG Software, and Frank Toth, Xilinx Inc. |
| 09/09/98 | Unexpected Device Speed Can Cause Problems | Peter Alfke, Xilinx Inc. |
| 09/02/98 | Using CPLDs to Simplify/Reduce Microcontroller Designs | Brent C. Douglas, Lattice Semiconductor |
| 08/26/98 | Incorporating Phase-Locked Loop Technology into Programmable Logic Devices | Greg Steinke, Altera Corporation |
| 08/19/98 | Faster Product Development and Easier Product Upgrades with In-System Programmability | Chris Schell, Philips Semiconductors |
| 08/12/98 | The Role of Intellectual Property in the System-on-a-Chip Revolution | Herman Beke, Frontier Design |
| 08/05/98 | A New Approach to Designing Digital Signal Processing Systems | Nick Lethaby, Elanix, Inc. |
| 07/22/98 | FIFO Applications Enabled by Embedded RAM in FPGAs | John Birkner, Vice President, co-founder, QuickLogic Corporation |
| 07/15/98 | Designing for Performance: CPLDs vs. FPGAs | Anita Schreiber, Philips Semiconductors |
| 07/01/98 | Tech Note Introduction | Murray Disman, Consulting Editor |
| 06/23/98 | DAC 1998 |
| 06/16/98 | Altera Forms IP Unit |
| 06/09/98 | Gatefield And Siemens Sign Foundry Agreement |
| 06/02/98 | New EDA Company, Axis Systems, to Offer New Verification Technology |
| 05/27/98 | Xilinx wraps up work at reconfigurable operation |
| 05/19/98 | Actel Agrees In Principle To Acquire AutoGate Logic |
| 05/12/98 | Xilinx, Insight open dedicated programmable logic training centers in Asia |
| 05/05/98 | Investors Chasing Too Few Net Stocks |
| 04/28/98 | Synopsys Realigns FPGA Sales Channels |
| 04/21/98 | The FCCM 1998 Conference |
| 04/14/98 | CPLD Customers Benefit From Intense Competition |
| 04/07/98 | Lucent to work with Chip Express on LPSC technology as part of investment deal |
| 03/31/98 | IP'98 Conference Report |
| 03/24/98 | Dr. Om Agrawal named Vice President and Chief Technical Officer of Vantis |
| 03/17/98 | Altera Opens European Tech Center |
| 03/10/98 | FPGAs Compete With Complex PLDs |
| 03/03/98 | FPGA '98 Conference Overview |
| 02/24/98 | Cypress adds 3.3-V compatibility to Flash370i family |
| 02/16/98 | All American to handle Clear Logic's low-cost ASICs |
| 02/09/98 | Stumbling Blocks on the Road to IP Reuse |
| 02/02/98 | DesignCon98 |