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  Programmable Logic

    Tech Notes Archive

Date Headline Author
03/11/03 The Benefits of FPAA Technology for Implementing Analog Designs Suhel Dhanani, Anadigm
07/16/02 Maximizing Embedded System Performance in the Era of Programmable Logic Altera Corp.
04/22/02DSP Design Using a True Top-down Design MethodologyAccelChip
01/21/02Design Security in Nonvolatile Flash and Antifuse FPGAsActel
12/11/01A Methodology for the Concurrent HW/SW Design of Programmable Systems-On-ChipsMartin Mason
10/24/01Implementing Control Logic in Today's "Multi-Voltage" SystemsSuhel Dhanani and Mr.Hiroyuki Yamashita
08/28/01Programmable Logic Facilitates the Implementation of OFDM Based SystemsTapan A. Mehta, Altera Corporation
08/28/01FPGAs Driving Voice-Data ConvergenceAmit Dhir, Xilinx Corporation
07/10/01Implementing LED Drivers in Product-Term Based PLDsFrederick Lo, Altera Corporation
06/09/01Transition of Broadband Access Devices to Residential GatewaysAmit Dhir, Xilinx Corporation
04/27/01Selecting the Right Two-Chip Solution for Embedded System DesignsMark Rootz, Applications Manager, STMicroelectronics PSM Division
03/27/01A Design Methodology for The Efficient Implementation of Complex DSP Algorithms in FPGAsJohannes Steensma, Frontier Design
02/23/01Using Product-Term Devices to Replace Discrete I/O DriversJennifer Stephenson, Altera Corp.
02/05/01A study of high-performance reconfigurable constant coefficient multiplier implementationsPhilip James-Roxby and Brandon J. Blodget, Xilinx, Inc.
12/29/00Programmable Logic and High-Speed Serial I/OsMurray Disman, eChips
11/30/00Support for Multiple I/0 Standards; Another Required Checkmark for Today's CPLDsSuhel Dhanani, Altera Corp.
11/12/00Guided Synthesis Using FPGA Express/FPGA Compiler II Block Level Incremental SynthesisKaren Fidelak, Xilinx, Inc
10/15/00Building Configurable Network ProcessorsHiro Higuma and Martin S. Won, Altera Corporation
09/18/00Using the Internet to Repair Hardware in the FieldNeil G. Jacobson, Xilinx, Inc.
08/07/00Newest FPGAs Designed to Support 160 Gbps Buffered Communications Crossbar SwitchesPeter Alfke, Xilinx, Inc.
07/21/00Programmable Logic and the Challenges of System-on-a-Chip DesignMartin Won, Altera Corporation
06/19/00Evolution of the Programmable Logic IndustryMurray Disman, ChipCenter's PLD Design Center
06/05/00Processing Digital Signals With Programmable Logic DevicesTony San, Altera Corporation
05/15/00PCI to Gigabit Tx/Rx Chipset ControllerBrian Faith, QuickLogic
05/01/00Using FPGAs to Build an MP3 PlayerRobert Bielby, Xilinx, Inc.
04/14/00Impact of DFT on Fault Coverage and Product Quality in SoC DesignsJon Turino, SynTest Technologies, Inc.
03/24/00New IP Evaluation Model Reduces Risk, Speeds FIR Filter Design Time for Communications Test EquipmentCharlie Evans and Jeff Fox
03/10/00Maximizing Intellectual Property Reuse for PCIBrian Faith and Mao T. Wang
02/21/00An Open System Approach For Verilog and VHDL DebuggingScott Sandler
02/04/00Configurable Logic For Digital CommunicationsChris Dick and Fred Harris
01/17/00Seizing Control of the Design ProcessViewlogic Systems, Inc.
01/05/00Evolving Verification Techniques in PLD DesignSuhel Dhanan
12/23/99Re-configurable Logic Cores for SOC Devices Mark Scheitrum
12/07/99Solidification ý Static Functional Verification with Solidify Graham Bell
11/29/99New LVDS Capabilities Giving 422 and 485 a Run for the MoneyKevin Gingerich
11/11/99The Future of System Design: Configurable Cores and CPLDsMartin S. Won, Bernie Rosenthal
10/28/99SEU Mitigation Techniques for Virtex FPGAs in Space ApplicationsCarl Carmichael, Earl Fuller, Phil Blain, Michael Caffrey
10/06/99Block-Based Prototyping MethodologyAptix Corporation
09/22/99Demystifying FPGA to ASIC ConversionBob Kirk, CAD Research Manager, American Microsystems Inc.
09/08/99Architectural Synthesis and Design Re-useMarc Van Canneyt, Vice President of Business Development, Frontier Design, Inc.
08/25/99Configurable Logic for Digital Signal ProcessingChris Dick, Bob Turney (Xilinx Inc.) and Ali M. Reza (University of Wisconsin)
08/03/99Reconfigurable High Speed Arithmetic Functions in a Non-Volatile FPGABy Rufino T. Olay III, QuickLogic Corp.
07/26/99Development of Reusable Algorithms Based on C and C++By Doug Johnson, Frontier Design, Inc.
07/09/99Incremental Synthesis and Place and Route using LeonardoSpectrumBy Tom Hill, Exemplar Logic
06/30/99The 1999 Design Automation ConferenceBy Murray Disman
06/14/99Increasing Importance of HDL VerificationBy Gregor Siwinski, Aldec Inc.
06/07/99FPGA-Based System Level IntegrationBy Joel Rosenberg, Atmel
05/12/99Remote Field Updates Using FPGAsBy Tom Branca, Chris Stinson and Brant Soudan, Xilinx, Inc.
04/29/99Improving Performance in Complex Programmable Logic Devices (CPLDs) with the FPGA Express SoftwarePhil Simpson, Altera Corporation
04/13/99A Cost Effective Image Acquisition, Real-Time Processing and Display Architecture Using FPGA TechnologyJohn Smith, Principal Engineer, VisiCom, and Sheldon Liebman, Industry Advisor
04/06/99IP'99 Conference ReportMurray Disman, Editor EDTN PLD Design Center
03/17/99Pipelined Design for CPLD Improves System PerformanceJimmy Gao, Lattice Semiconductor Corp.
03/10/99Integrating Multiple CPLD Functions in an Actel SX DeviceLone Star Logic, Inc.
02/24/99The Programmable Logic Proving GroundTom Troksa, Packet Engines (part of Alcatel), Steve Dabell, Packet Engines, and Martin S. Won, Altera Corp.
01/20/99New FPGA Architectures Address Wide Gating FunctionsOm Agrawal and Bill Harding, Vantis Corp.
01/13/99Accelerating DTP with Reconfigurable Computing EnginesDonald MacVicar, The University of Glasgow and Satnam Singh, Xilinx Inc.
12/16/98Optimal HDL Coding Styles for Programmable Logic DesignSuhel Dhanani, Altera Corporation
12/16/98BoardScope: A Debug Tool for Reconfigurable Systems (.pdf formate)Delon Levi and Steven A. Guccione, Xilinx, Inc.
12/09/98Fibre Channel Multimedia Adapter With PCI Bus Interface Using ORCA FPGAsAlan Cunningham, Lucent Technologies
12/02/98PCI Bus Target Controller Implementation Using a Lattice ispLSI CPLDBertrand Leigh, Lattice Semiconductor
11/11/98Automatic Hardware Synthesis for a Hybrid Reconfigurable CPU Featuring Philips CPLDsBernardo Kastrup, Philips Research Laboratories
11/04/98Error Control Coding Functions in Programmable LogicTapan A. Mehta, Altera Corporation
10/28/98FPGA Large Device Design MethodologyTom Hill, Exemplar Logic
10/21/98An Emerging Solution For Embedded System DesignChris Balough, Triscend Corp.
10/14/98Combining FPGA Cores To Extend The Performance Of DSP DesignsPaul Laity and Sabine Lam, Xilinx, Inc.
10/07/98Meeting the Synthesis Challenge of Complex Programmable Devices at 100K gates and BeyondDarron May, ALT Technologies
09/23/98Implementing 155 Mbps ATM in High-Speed, High Density, FPGAs with On-Chip RAMJoaquin Aviles of Cisco Systems Inc. & Brian Faith of QuickLogic Corp.
09/16/98The Java API for Boundary-ScanNeil Jacobsson, JTAG Software, and Frank Toth, Xilinx Inc.
09/09/98Unexpected Device Speed Can Cause ProblemsPeter Alfke, Xilinx Inc.
09/02/98Using CPLDs to Simplify/Reduce Microcontroller DesignsBrent C. Douglas, Lattice Semiconductor
08/26/98Incorporating Phase-Locked Loop Technology into Programmable Logic DevicesGreg Steinke, Altera Corporation
08/19/98Faster Product Development and Easier Product Upgrades with In-System ProgrammabilityChris Schell, Philips Semiconductors
08/12/98The Role of Intellectual Property in the System-on-a-Chip RevolutionHerman Beke, Frontier Design
08/05/98A New Approach to Designing Digital Signal Processing SystemsNick Lethaby, Elanix, Inc.
07/22/98FIFO Applications Enabled by Embedded RAM in FPGAsJohn Birkner, Vice President, co-founder, QuickLogic Corporation
07/15/98Designing for Performance: CPLDs vs. FPGAsAnita Schreiber, Philips Semiconductors
07/01/98Tech Note IntroductionMurray Disman, Consulting Editor
06/23/98DAC 1998
06/16/98Altera Forms IP Unit
06/09/98Gatefield And Siemens Sign Foundry Agreement
06/02/98New EDA Company, Axis Systems, to Offer New Verification Technology
05/27/98Xilinx wraps up work at reconfigurable operation
05/19/98Actel Agrees In Principle To Acquire AutoGate Logic
05/12/98Xilinx, Insight open dedicated programmable logic training centers in Asia
05/05/98Investors Chasing Too Few Net Stocks
04/28/98Synopsys Realigns FPGA Sales Channels
04/21/98The FCCM 1998 Conference
04/14/98CPLD Customers Benefit From Intense Competition
04/07/98Lucent to work with Chip Express on LPSC technology as part of investment deal
03/31/98IP'98 Conference Report
03/24/98Dr. Om Agrawal named Vice President and Chief Technical Officer of Vantis
03/17/98Altera Opens European Tech Center
03/10/98FPGAs Compete With Complex PLDs
03/03/98FPGA '98 Conference Overview
02/24/98Cypress adds 3.3-V compatibility to Flash370i family
02/16/98All American to handle Clear Logic's low-cost ASICs
02/09/98Stumbling Blocks on the Road to IP Reuse
02/02/98DesignCon98

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