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Spartan-3 on 90 nm

The manufacturer says . . . Murray Disman says . . .

Xilinx Targets $23 billion Market with 90 nm Spartan-3 Programmable Chips
Xilinx Combines 90 nm and 300 mm Manufacturing Technologies to Set a New Price-Density Standard for Programmable Chips—Customers Embrace Cost Benefits
SAN JOSE, Calif.--April 14, 2003--Marking a major milestone in the semiconductor industry, Xilinx, Inc. unveiled a new family of programmable chips expected to propel programmable logic devices further into high-volume, low-cost applications traditionally served by custom chips with fixed architectures. With the new Spartan-3 family, Xilinx is leveraging both 90 nm* and 300 mm* advanced manufacturing technologies to achieve unprecedented density and price for field-programmable gate arrays (FPGAs). By setting a new FPGA price-density standard, Xilinx will be able to target a $23 billion** total available market (TAM) and address new higher volume applications in the application-specific integrated circuit (ASIC) market.
Xilinx's investment in the world's most advanced 90 nm and 300 mm chip-making process with dual fabrication partners IBM and UMC has enabled the company to achieve an 80 percent chip-size reduction compared to competitive products on 130 nm technology. With prices starting at under $3.50***, Spartan-3 platform devices range from 50K to 5M system gates. Spartan-3 is the world's lowest cost FPGA family, with pricing at under $20*** for a one-million-gate FPGA, and under $100*** for a four-million-gate FPGA—a cost savings of up to 80 percent over competitive offerings. Already, Xilinx has shipped Spartan-3 devices to customers from both fabrication partners.
Industry Leaders Race to Advanced Process and Manufacturing Technology
Xilinx joins other leaders in their respective industries—industry giants such as IBM, Intel, and Texas Instruments—in spearheading the adoption of 90 nm and 300 mm manufacturing technologies to further separate themselves from the competition by taking advantage of the greatest cost reductions in recent semiconductor history.
"The companies that get into 90 nm production first will get a tremendous advantage in lower cost due to higher yields. The die shrink can also lead to much higher performing devices," said Dan Hutcheson, president and CEO at VLSI Research Inc., San Jose. "Rivals who are late in 90 nm process technology will fall behind and may not be able to catch up." According to public statements, Xilinx's nearest competitor will not ship 90 nm products until the first half of 2004, giving Xilinx a formidable lead in 90 nm and its customers an added edge.
"With today's announcement, Xilinx has completely changed the economic playing field for FPGAs, opening up a vast new market opportunity. Now, designers can afford to choose FPGAs over traditional custom devices for a broader set of cost-sensitive, high-volume applications—and get to market faster," said Wim Roelandts, president and CEO of Xilinx. "As traditional ASIC and ASSP design starts continue to decline, we expect that FPGA design starts using Spartan-3 will ultimately fuel higher growth for PLD makers."
Spartan-3 FPGAs: ASIC Replacement for High-Volume Applications
Engineers developing products for the price-sensitive, high-volume electronics market have historically used custom chips with fixed architectures such as ASICs because of their performance and cost advantages. With Spartan-3, Xilinx has dramatically narrowed the price-performance gap between programmable and fixed logic to drive FPGA adoption further into higher volume applications and hasten the decline of ASIC design. Among the many applications Xilinx can now address are low-cost routers, storage servers, residential gateways, medical and industrial imaging, video-on-demand services, and consumer entertainment (LCD TVs, HDTV, DVD-RW, etc.), to name a few. In addition, by making programmable technology more affordable and accessible, new types of functionality and features will now be available in a wider range of end products.
Richard Wawrzyniak, senior analyst for ASICs and SoCs (systems-on-a-chip) at Semico Research Corporation agrees. "With today's announcement of low-cost FPGAs, Xilinx is positioned to initiate a new wave of innovative solutions aimed at empowering a whole range of applications that previously could not use FPGAs. The design alternatives open to engineers have been expanded by the new Spartan 3 family of FPGAs due to their high functionality, off-the-shelf availability, and low cost structure; and clear advantages over custom ASICs when the major concern is to reduce costs and get to market faster."
Spartan-3 Platform: Built on Foundation of Customer Success
The new 90 nm Spartan-3 platform has been built on the proven success of Spartan Series products, which have been broadly adopted in high-volume, high-growth consumer applications—the most difficult high-volume market to penetrate and one historically dominated by ASICs. Since its introduction in 1998, Xilinx has shipped more than 50 million Spartan Series devices that have been designed into innovative products ranging from set-top boxes and plasma-display televisions to automotive telematics.
"Xilinx Spartan Series FPGAs provided a cost-effective, programmable alternative to ASICs," said Richard Beckert, hardware design lead at Microsoft Corp. "We chose the Spartan series FPGA because it provided us with a time-to-market advantage, the flexibility to make last-minute changes, as well as impressive product support from Xilinx."
Pricing and Availability
The new Spartan-3 family consists of eight devices at prices starting below $3.50. First customer shipments of new Spartan XC3S50 (50K system gates for under $3.50), and XC3S1000 (1 million system gates for under $20) began last month. Additional family members will begin shipping in the summer of 2003. The entire Spartan-3 family will be available in volume production in early 2004 from distributors worldwide, or direct from Xilinx at www.xilinx.com/spartan.

Xilinx first announced that it was sampling a new family made on a 90 nm process about two weeks ago. It has now identified the new family as the Spartan-3 series.
The company has made a monstrous jump by migrating its Spartan family from a 180/150 nm hybrid process for the 1.8 V Spartan-IIE to a 90 nm process for the 1.2 V Spartan-3 family. This announcement is not the typical Xilinx "shoot for the stars" performance release—Spartan-3 has been specifically designed for low cost.
Recent releases by Xilinx and its fab partners, IBM and UMC, have prompted responses from TSMC (see TSMC Claims 130 nm Lead) and Altera, Xilinx's primary competitor.
While the new family will offer Virtex-II-like speeds, its performance is far from what could have been achieved at 90 nm with a low-k dielectric. To be fair, the new family was intentionally designed with slower high-Vt transistors to keep leakage currents under control.
Spartan-3 is really a shrink of Virtex-II with proportionally fewer embedded memory blocks and embedded multipliers. In addition, only 50% of the Spartan-3 LUTs can be used for distributed memory, and the speed of the differential LVDS I/Os has been capped at 622 Mbits/s, compared with 840 Mbits/s for Virtex-II.
The Spartan-3 family contains eight members ranging in capacity from 1,728 to 74,880 logic cells. The smallest part, the XC3S50, does not contain any embedded memory blocks or embedded multipliers. This is somewhat surprising since the Spartan-IIE XC2S50 did have 32 kbits of embedded memory.
On the other hand, the capacity of the largest Spartan-3 device is nearly five times larger than that for Spartan-IIE. The largest Spartan-3 part, the XC3S5000 with 74,880 logic cells, is only moderately smaller than the largest Virtex-II device, the XC2V8000, with about 104K logic cells.
The 90 nm process yields some very small die. For the first time, Xilinx is using a dual ring of staggered I/O pads to minimize die area. This is a technique that has been used by ASIC suppliers for some time. Xilinx claims that the prices for the smaller members of the Spartan-3 family will be 30% to 40% less than the corresponding Spartan-IIE parts. This decrease in price is what would be expected.
The real surprise is Xilinx's expectation that the price of the larger Spartan-3 devices will be 70% to 80% less than that of a comparable-capacity Virtex-II part. Spartan-3 will prove to be a very attractive alternative to Virtex-II—but we haven't heard about Virtex-III yet.
Xilinx is currently sampling the XC2S50 and the XC2S1000. It plans to start sampling all the other devices in the family during 2H03, and to be in production on some parts by the end of 2003 using 300 mm wafers. The samples now being shipped are being produced on 200 mm wafers.
Spartan-3 is a prime example of the benefits that FPGAs can bring to the designer. By concentrating on using the most advanced process technologies, Xilinx has been able to supply FPGAs well in advance of 90 nm ASSP or ASIC availability. It has, according to the company, solved the packaging, signal-integrity, and leakage-current problems associated with producing devices at this node.
Spartan has been a success at Xilinx. The family now accounts for nearly 17% of total revenue, up from 11% last year, and has grown at 10% per quarter over the past several quarters. Some 53 million Spartan devices have now been shipped. The growing importance of the family is demonstrated by the fact that, for the first time, Spartan is being built on the most advanced process in use at Xilinx.
PLD growth has shifted from telecommunications to that of consumer-oriented electronics. Spartan-3 will serve this area and will also be adopted by almost all other FPGA application areas. The new family is in line to become the flagship product at Xilinx. It is too bad we have to wait almost two years before the promised low prices kick in.

* 90 nm measures the space between the lines of circuitry on a chip, and is less than 1/1,000th the width of a human hair.
300 mm wafers describe the diameter of the silicon disk used to produce chips. The larger the surface, the more chips that can be produced per wafer.

** Sources: iSuppli 1/2003; Dataquest 2/2003

*** Pricing in quantities of 250,000 in volume production in 2004.

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