The manufacturer says . . .

Murray Disman says . . .

SAN JOSE, Calif., March 4 Xilinx, Inc., the leader in programmable logicsolutions, announced today that it is shipping the Virtex-II Pro FPGAfamily: the world's first FPGA to immerse high performance IBM PowerPCprocessors in the Virtex-II fabric with multi-gigabit serial transceivers tosolve high-performance architectural challenges. Using its patent-pending IPImmersion technology, Xilinx has integrated these two essential requirementsfor next-generation systems, RISC processing and high-speed serialtechnology, in the popular Virtex-II fabric, which includes the advancedActive Interconnect, BlockRAM, and clock management features. Thisunprecedented level of integration offers systems designers the highestlevel of performance with the lowest system cost available from anyprogrammable solution.

"The Virtex-II Pro family represents one of the most significant productintroductions for Xilinx since inventing the FPGA in 1984. It shifts theusage model for programmable technology from logic to systems," said WimRoelandts, Xilinx president and CEO. "With new Virtex-II Pro FPGAs, systemdesigners can leverage the advantages of programmability at thearchitectural level. Virtex-II Pro family represents the fruition of decadesof experience in microprocessor from IBM, high-speed serial from Conexant,development tools from Wind River, and our programmable logic technologies.Xilinx partnered with leaders in each of these areas to deliver arevolutionary product."

"Because we had access in advance to the preliminary information for theXilinx Virtex-II Pro FPGAs, we were able to evaluate the architecture forour needs," Mr. Stefano Gastaldello, Optical Multiserve Networks/ASICs labmanager, Alcatel, Italy. We've verified and are encouraged that it matchesvery well with the architecture of our next generation of high capacityoptical multiservice nodes and gateways."

Industry leaders collaboration

IBM and Xilinx collaborated to immerse the leading embedded processorarchitecture, the IBM PowerPC, in the Virtex-II fabric. The Virtex-II Profamily supports up to four PowerPC 405 processor cores each running at up to300 MHz. The Xilinx immersion method allows hard IP cores to be diffused atany coordinate within the Virtex fabric while maintaining smooth integrationwith the surrounding array. IP Immersion technology intimately couples allof the high-speed buses on the core directly to the programmable fabricgiving significantly higher system-level performance than an equivalentdiscrete processor.

"Combining our respective leadership technologies in programmable logic andRISC processor cores is the natural next step in high-performance embeddedsystem design," said Ron Tessitore, vice president, PowerPC andNetworkingTechnology Development, IBM Microelectronics. "The popularity andwidespread acceptance of the IBM PowerPC family underlines the success ofthe architecture for networking, communications, pervasive computing, andIT/storage applications. The synergy with Xilinx is borne in the successfuldelivery of this revolutionary semiconductor family."

First with Multi-gigabit serial I/O support

Virtex-II Pro FPGAs also feature RocketIO technology, the first multi-port,3.125 Gb/s serial interface available in a programmable solution. Thiscombination represents a complete solution for high-performance interfacestandards such as Gigabit Ethernet, 10 Gigabit Ethernet, 3GIO, SerialATA,Infiniband, and FibreChannel. Based on an enhanced version of the provenConexant SkyRail technology, the gigabit serial interface significantlysimplifies integrating high-bandwidth interfaces. System designers have oneplatform that delivers emerging connectivity standards and allows them toincrease their I/O performance.

World-class development tools

Software development, hardware development, and system integration solutionsinclude compilers and integrated development environments from Wind Riverand GNU. The Xilinx System Generator for PowerPC tool automatically buildscustom PowerPC processor systems with Xilinx Virtex-II Pro FPGAs. The SystemGenerator for PowerPC tool enables designers to architect, customize, andgenerate the hardware and software components for an entire processorsystem. Hardware debug options are also available from Wind River andAgilent. The new tools, coupled with Wind River embedded software tools,free GNU tools and ISE 4.2i logic design tools from Xilinx, providecustomers with access to a complete tool chain for rapidly buildingprogrammable systems.

New Development Paradigm and On-Demand Architectural Synthesis

The combination of the programmable system platform with next generationsystems development tools enables a new development paradigm capable ofrunning hardware and software in situ at speed with real-time observability.This results in significant reduction in system design verification timeleading to faster time to production. In addition, development teams canprovide dedicated hardware early in the development cycle to softwareengineers, further reducing design time and development cost for highperformance systems.

Beyond this, the use of behavioral synthesis technologies enables On- DemandArchitectural Synthesis, which provides the capability to optimize thesystem architecture for an application. This includes the mix of hardwareelements as well as hardware/software partitioning. On-Demand ArchitecturalSynthesis allows partitioning for optimal system performance duringdefinition, during debug, and after product shipment. Designers can now getthe performance they need without costly and time-consuming re-designs.

System-level price/performance leadership

In addition to flexibility and power in Virtex-II Pro FPGAs, the high levelsof system integration with RocketI/O and processor technologies enabledramatic system cost reduction. The XC2VP4, the XC2VP7, and the XC2VP20devices are available now. The remaining members, the XC2VP2 and XC2VP50will be available in mid-2002. High-volume pricing (25,000 units) in 2004for the XC2VP4, XC2VP7, and XC2VP20 devices is $120, $180, and $525,respectively.

Xilinx's Virtex-II Pro familysets a new performance standard for the PLD industry in terms of combining I/Ospeed and embedded processing power. Actually, the Virtex-II Pro 3.125 Gbits/sI/Os are matched by the ORCA ORT82G5,devices that Agere announced were being shipped nearly one year ago. Few ofthese parts have been delivered, but this could change now that Lattice ownsthe ORCA product line.

Xilinx has been sampling Virtex-II Pro parts since December 2001, which isbehind the delivery schedule announced earlier in the year. Some 20customers have been working with devices and a beta version of the company'sIntegrated Software Environment (ISE) 4.2i design system. ISE 4.2i has nowbeen released with the announcement that all of the ISE implementation toolsnow run on Linux RedHat version 7.2 with the Wine applications layer.Xilinx expects that later versions of ISE will move to native Linux in 2003.

Virtex-II Pro is basically a 0.13-micron, 9-layer copper metal, version ofVirtex-II with changesin the amount of embedded Block RAM and the addition of the embedded PowerPCprocessor and the Conexant-based 3.125 Gbits/s serial I/Os. Xilinx claims thatthe Virtex-II Pro's FPGA performance is 20% to 30% faster than that of theVirtex-II. This is a much greater improvement than one would expect justfrom a shrink from 0.15 micron to 0.13 micron.

There are five members in the Virtex-II Pro family with logic cell densitiesranging from 3.2K to 50.8K cells. The two smallest family members containfour 3.125 Gbits/s I/O transceivers, the next two have eighttransceivers, and the largest device has 16 of the high-speed serial I/Oblocks. The smallest part does not contain a PowerPC processor. The nexttwo larger parts contains single processors. Two processors are embedded inthe next larger part and the largest part in the series contains fourprocessors.

The changes in embedded block memory from the Virtex-II family are a littlepuzzling. The largest Virtex-II Pro has nearly twice as much memory as theclosest Virtex-II device, the XC2V4000, while the smallest Virtex-II Propart, the XC2VP4, has only one-half the memory of the closest Virtex-II.The middle-size Virtex-II Pro part has about the same amount of memory asthe corresponding Virtex-II FPGA. One would have expected very largeincreases in embedded block RAM to store processor instructions and data forthe two parts that contain a single PowerPC.

The closest competitive FPGA is Altera's ARM922T-based Excalibur family. The largestExcalibur part, the EPXA10, with 38.4K logic elements, has been shipping fornearly one year. The other two family members, the EPXA4 and the EPXA1,were just released.

There are major differences in the design philosophies used in Virtex-II Proand the ARM-based Excalibur devices. One is the placement of the processorwith respect to the FPGA fabric. Altera placed the embedded processor atone edge of the chip, while Xilinx embedded the PowerPCs in the heart of theFPGA fabric.

An even more important difference is the amount of resources embedded withthe processor. The embedded PowerPC includes 16 Kbyte instruction and datacaches and instruction and data on-chip memory controllers. All otherPowerPC peripherals, plus the CoreConnect bus, must be implemented as softmacros from Xilinx's new System Generator for PowerPC software.

The tool is to be released during 2Q02 along with some 40 IP cores thatinclude cores for arbiters, bridges, and memory controllers for theCoreConnect bus. In addition, the library will include UART, I2C, ATM andEthernet peripheral cores, plus PowerPC boot code, board support packages,test code, device drivers, and RTOS support. Designers will have to use aXilinx version of the GNU tools until the System Generator for PowerPC tooland library is released.

While Xilinx has opted for flexibility with its soft bus and peripherals,Altera has chosen to embed a complete processor subsystem in Excalibur. Anembedded AMBA high-speed processor bus and an AMBA peripheral bus, which canrun at 100 MHz, tie the elements of the subsystem together. The peripheralbus is used to interface with the FPGA fabric.

The processor subsystem in the largest Excalibur part includes 256 Kbytes ofSRAM and 128 Kbytes of dual-port SRAM. The total amount of embedded memoryin Altera's single processor Excalibur device is almost equal to the amountof embedded memory in Xilinx's four-processor Virtex-II Pro.

Altera claims that its approach, with an independently bootable subsystem,is much easier for the designer to use. In addition, the company assertsthat its embedded debug and trace circuitry are important aids in debuggingthe processor software.

The Excalibur and Virtex-II Pro devices will serve different segments of theembedded system market place because of the processors used. Virtex-II Pro,with the PowerPC and 3.125 Gbits/s I/Os, is aimed directly at high-speednetworking applications, where it will be used for such functions as runningthe protocol stacks and header file processing. The MAC/link layer will beimplemented in the FPGA fabric.

The PowerPC is more popular in networking applications than ARM processors.Altera's ARM-based Excalibur family, however, will appeal to a much largerbase of users, especially in Europe. As a result, Altera is uncovering newcustomers for its products. This is all well and good, but it should beremembered that networking applications account for more than one-half ofthe FPGA market.