The ispXPGATM (in-system programmable eXpanded Programmable Gate Array) family combines on-chip E2 memory with SRAM cells in a non-volatile architecture which allows infinite reconfiguration. This unique marriage of technologies is named ispXP, for eXpanded Programmability. Since the ispXP devices in the ispXPGA family self-configure in microseconds at power-up ("Instant On"), they are available to an electronic system during its power-up sequence. The products are highly secure, as well, since on-chip E2 memory means no external bit stream is exposed during configuration, and security bits can inhibit FPGA pattern readback. The family is supported in Lattice's ispLEVER integrated, hierarchical CPLD/FPGA design software.

"Lattice is excited to bring innovative programming technology to the FPGA market with a complete, mainstream product offering," said Steven A. Laub, Lattice's President. "Our unique value for customers with our Non-Volatile/Infinitely-Reconfigurable/Instant-On approach overcomes the deficiencies of conventional SRAM FPGAs."

ispXPGA CapabilitiesThe features most sought by users in an FPGA are all built into the ispXPGA family. These include:

A versatile PFU (Programmable Function Unit)

Hardware-accelerated arithmetic and muxing that enhance performance

Distributed single-port, dual-port, FIFO, and shift-register memory for local scratchpad needs

Wide-gating expansion for operations with up to 20 inputs

Two Flip-Flops per Look-Up Table that improve efficiency/speed of library elements, pipelining, and register-retiming for boosting fMAX

sysMEM embedded 4k-bit memory blocks

Single-port, dual-port, and FIFO configurations

Parity provided for with x9 and x18 support

Variable-Length-Interconnect optimized for performance and efficiency

sysIO input/outputs giving the user a choice of dozens of I/O types for single-ended and differential needs meeting industry standards for varied applications

sysCLOCK phase-locked-loops (PLLs)

Clock frequency synthesis

Multiple clock generation

Clock alignment at either board or device level

Programmable delay for fine-tuning of clock signals in 250ps increments

sysHSI (High-Speed Interface) 850 Mbit I/Os with SERDES and clock recovery for handling ultra-fast data streams

1.8/2.5/3.3V operation for users' choice of most convenient power supply

The ispXPGA FamilyThe ispXPGA family covers 125K gates to 1.2M gates or 2K to 15K logic elements. Gates are counted using the industry-standard approach. Block RAM goes from 92K to 414K bits, while Distributed RAM reaches from 30K to 246K bits. The family has products from 160 to 496 I/Os, including 4 to 20 sysHSI clock pairs. This range of resources addresses the vast majority of customer design needs. The ispXPGA family is complemented by Lattice's new ispXPLD family, also with ispXP technology, announced today.

ispLEVER Software - "The Simple Machine for Complex Design" Release 2.0 of the Lattice ispLEVER design software includes complete support for the ispXPGA and ispXPLD families, as well as ORCA Field Programmable System Chips (FPSC), ispMACH CPLDs, ispGDX crosspoint switches, and ispGAL SPLDs. Tools added to the ispLEVER software for the ispXPGA family include a floorplanner, timing-driven place and route, a module compiler, core manager, enhanced constraint editor, and expanded timing analysis, plus HTML report browsing.

The overall user interface of the ispLEVER software carries on from prior releases. This maintains the design environment customers are familiar with, and avoids unnecessary new learning. This means customers can get started quickly with v2.0.

Users' preferred HDL design flows are provided for through Lattice's relationship with major EDA tool suppliers. HDL synthesis support is available for Exemplar Leonardo Spectrum, Mentor Design Architect, Synopsys Design Compiler, and Synplicity Synplify. Simulation support is available for Cadence Verilog-XL; Mentor ModelSim, QuickSim, and QuickVHDL; Synopsys VSS and Chronologic; Viewlogic ViewSim; and multiple sources of VHDL/Vital. Board-level verification support is available for Mentor/Telalogic Tau, Synopsys PrimeTime, and Viewlogic Blast.

Intellectual Property (IP) CoresLattice has developed in-house LeverCORE IP Cores for our customers. These Cores are aimed at Bus, Communications, Memory, and DSP applications. They are parameterized so users can get the Core functionality they desire.

Price and Availability

The initial ispXPGA device to be offered is the 1.2 million gate product, which is called the LFX1200 (Lattice, FPGA Product Line, ispXPGA Family, 1200 K-gates). It is being made available in Commercial (0ºC to 70ºC) and Industrial (-40ºC to +85ºC) temperature grades as well as 1.8V and 2.5/3.3V power supply versions. Samples will be available later in Q3 with production in Q4. It comes in a 900-ball fine-pitch BGA package or a 680-ball thermally-enhanced fine-pitch BGA package. The LFX1200 is priced at $345 per device in thousands.

Lattice has three features in their ispXPGA FPGA offering that distinguishes the new family from the devices being produced by Altera and Xilinx - the main SRAM-based FPGA suppliers. These are the inclusion of an EEPROM to hold the configuration data for the SRAM, the ability to operate the FPGA core at three different voltages, and a logic cells that contains a four-input LUT and two registers. These three features will provide an advantage for Lattice's FPGAs in certain specific situations, but not across the board.

Standard SRAM-based FPGAs require that the configuration data be loaded from an external memory when the device is turned on. This creates a number of problems that include the need to provide for the storage of the configuration data, the time required for loading the SRAM can be seconds, and the configuration bit stream can be captured to copy the design. There are a number of PLDs on the market that can eliminate these problems, but have other drawbacks.

CPLDs usually contain EEPROMs that store the configuration data, but these are limited in the number of times that they can be programmed. Antifuse FPGAs from Actel and QuickLogic do not have these shortcomings, but they are one-time programmable. Actel's flash-memory-based ProASIC FPGAs do not require external memory, but are guaranteed for only 100 programming cycles.

The only available device that has the versatility of Lattice's ispXPGA family is one of Atmel's FPSLIC parts. This programmable device contains two chips in a single package. One chip consists of an FPGA with an embedded microcontroller. The other chip is a flash memory device that holds the configuration data for the FPGA.

The closest device to Lattice's new family, in terms of security and reprogrammability, is Actel's ProASIC series. While the ProASIC parts can be reprogrammed in the field to account for design changes and upgrades, the limits on programming cycles eliminate them from consideration for applications that depend on continually reconfiguring the device's logic.

An on-chip regulator allows the use of 1.8V, 2.5V, or 3.3V for the logic core's power supply. It is possible, at the same time, to set each of the eight I/O banks to different signaling voltages. According to the company, this flexibility has proven to be an important benefit to many designers.

Vantis (now part of Lattice) was the first to use a voltage regulator in a PLD - its MACH 4000 family. Lattice has continued this trend and is using the regulator in its latest CPLD family, the ispXPLD 5000MX family (see the following item). None of the other FPGA producers has considered this multi-voltage capability for the logic core as a worthwhile feature.

The use of two registers in each of the logic cells is another differentiator for the new Lattice family. Lattice claims that this feature "improves the efficiency/speed of library elements, pipelining, and register-retiming for boosting fMAX." It is not clear whether the additional silicon required for this feature makes it worthwhile for a broad range of applications.

The company claims that the use of a four-input LUT has yielded good quality results when using available synthesis tools. However, synthesis tools do not yet contain the algorithms that would take optimum advantage of the dual-register logic cells and other features in the new Lattice devices. These third-party design tools have been honed for the four-input LUT/register logic cell that is used by both Altera and Xilinx. It will take some time for commercial synthesis tools to reach this level of refinement for the ispXPGA architecture.

The ispXPGA family is primarily targeted at competing with Xilinx's Virtex-II devices. Lattice claims that the performance is competitive, even though its new family is built using a 0.18-micron process versus 0.15 micron for Virtex-II. Lattice's new FPGAs do not contain the complete embedded multipliers found in Virtex-II, Virtex-II Pro and in Altera's Stratix devices.

Lattice has paid attention to the current needs of the engineer in regards to I/O design. The company's sysIO Blocks contain input and output registers and the I/Os can be set to meet a wide variety of signaling standards. In addition, the ispXPGA devices contain from 4 to 20 dedicated differential I/O pairs with embedded SERDES and PLLs. The differential I/Os can support either the source synchronous or clock-data recovery (CDR) transmission modes at 850 Mbps. A shortcoming of the Lattice I/Os, compared to Virtex and Stratix, is the need to use external terminating resistors on the general purpose I/Os.

The density range covered by the four parts in the ispXPGA series is much narrower than the Virtex-II family. The smallest ispXPGA device is more than three times larger than the smallest Virtex-II part, and the largest Lattice FPGA, the LFX1200, is about one-fifth the size of the largest Virtex-II device.

Lattice's aims for its new line of FPGAs are fairly modest. The company does not want to compete head-on with Altera or Xilinx and is looking to attract designers because of the special features in the ispXPGA series.