The ispXPLD family also utilizes Lattice's new ispXP (ISP eXpanded programmability) technology that combines the traditional product-term based PLD benefit of "instant-on", non-volatile programming together with real time, unlimited reconfigurability found in SRAM-based FPGAs.

"This breakthrough architecture provides a convergence of device architecture and programming technology that will allow ispXPLD devices to cross over traditional programmable logic segment boundaries," stated Steven A. Laub, President of Lattice Semiconductor. "We now have devices that combine the speed, predictability and non-volatility of CPLDs together with the system-level features, density and reconfigurability of FPGAs. System designers will no longer have to compromise one for the other. As such, Lattice ispXPLD devices signal the start of a third wave of PLDs, destined to succeed its Simple PLD and Complex PLD predecessors."

The initial series of ispXPLD devices, the ispXPLD 5000MX family, will be available in 1.8, 2.5 and 3.3 Volt power supply versions, designated the 5000MC, 5000MB and 5000MV series. The devices will be offered in 256, 512, 768 and 1024 macrocell-equivalent densities with 141 to 381 user I/O, corresponding to 75K to 300K system gates. The first device, the ispXPLD 5512MX, packaged in a 484 fine pitch BGA (fpBGA) package, will sample shortly.

Programmable sysIO interface capability provides flexible advanced I/O standard (GTL+, HSTL, SSTL, LVDS, etc.) support. Advanced silicon technology, combined with proprietary circuit design techniques, provides standby power consumption as low as 36 milliwatts per device for power-sensitive applications. Each device also incorporates Lattice's sysCLOCK PLL capability for high-performance on-chip clock synthesis.

The mix of system-level functionality, memory and logic allows the ispXPLD devices to address mainstream system functions previously relegated only to FPGAs or ASICs. Potential application areas include high-performance bus bridges, intelligent backplane interfaces, protocol processors and the like.

Multi-Function Block Implements Macrocells or Memory EfficientlyThe homogeneous ispXPLD architecture consists of a number of uniform Multi-Function Blocks interconnected by a single-level, high speed programmable Global Routing Pool (GRP). The GRP also connects the MFBs to the I/O cells. Devices in the ispXPLD 5000MX family integrate from 8 to 32 MFBs into a single device. Each MFB within an ispXPLD device can be programmed independently to implement 32 macrocells of SuperWIDE logic, an 8 kilobit Dual Port RAM, a 16 kilobit Single Port RAM or FIFO, or a 128 by 48 bit Content Addressable Memory (CAM). Dedicated FIFO control logic is included on-chip so programmable resources are not consumed providing these memory control functions. While the basic logic block configuration supports up to 68 logic inputs in a single level of logic, cascading MFBs allow the devices to support functions of up to 136 inputs without incurring an additional level of logic delay, further raising the bar for a wide logic architecture.

sysIO and sysCLOCK
Capability for Board-Level PerformanceEach I/O pin on the devices can be configured to support high-speed memory interfaces, advanced bus standards, or general-purpose interfaces. General-purpose interface support includes LVTTL or LVCMOS (3.3, 2.5 or 1.8 Volts). Four independent I/O banks provide support for multiple interface voltages and standards on a single device. Programmable drive levels for these standards facilitate the elimination of series termination resistors, further reducing overall system cost.

Interface to high speed DRAMs, SRAMs, and other high performance memory devices is made possible with SSTL2, SSTL3, and HSTL I/O support. The family also supports GTL+, PCI, LVDS and LVPECL I/O configurations for use in high-speed bus interfaces.

The ispXPLD devices have two sysCLOCK PLLs that provide precise timing control for today's high-speed designs. Designers can generate complex clock waveforms with the clock multiply and divide capability of the phase-locked loops, as well as adjust setup, hold and clock to output timings by shifting the clock under sysCLOCK control.

IspXP Technology - Non-Volatile and Infinitely ReconfigurableLattice's new ispXP technology enables its ispXPLD family (as well as its ispXPGA FPGA devices being concurrently introduced) to combine programmability benefits found in both non-volatile PLDs based on electrically erasable technology as well as reconfigurable FPGAs based on SRAM technology. As a result, the devices feature: (i) "instant on" operation at system start-up, allowing them to support critical system "heartbeat" functions without external initialization; (ii) non-volatile in-system programming, thereby giving higher integration through the elimination of an external boot PROM; (iii) enhanced design security since programming bit streams are invisible at system initialization; and, (iv) infinite reconfigurability via an 8-bit microprocessor port or JTAG boundary scan port for the ultimate in system adaptability.

Design Tools
The ispXPLD 5000MX family is supported by Lattice's new ispLEVER v2.0 design tools. The ispLEVER tools, Lattice's platform for next-generation logic design, provide designers with rapid access to the performance and features of the ispXPLD devices while maximizing resource utilization. This is achieved through timing driven placement & routing coupled with optimized synthesis support from vendors such as Mentor Graphics/Exemplar and Synplicity.

Additional third-party EDA tool support is provided through industry standard EDIF netlist import and export. The ispLEVER software is available in PC as well as UNIX workstation versions. The ispLEVER design tools, including VHDL and Verilog synthesis tools, are available for download from the Lattice website.

The most interesting feature of the ispXPLD 5000MX family is its ability to trade off programmable logic for memory functions. The device does not use embedded SRAM blocks, but instead is able to configure the logic circuitry contained in the multi-function blocks (MFB) as single-port RAM, dual-port RAM, FIFO, or CAM. This feature will prove to be attractive in many applications requiring a modest amount of programmable logic.

The new series of CPLDs is an extension of Lattice's SuperWIDE architecture. Each MFB contains 32 macrocells with 68 inputs from the Global Routing Pool. Adjacent MFBs can be cascaded to create a block with 136 inputs. Each MFB contains a programmable AND-array with 160 logic product terms and four control product terms.

Lattice has opted to use the same ispXP programming architecture in the ispXPLD as in the ispXPGA family. This, according to the company, "combines the traditional product-term based PLD benefit of "instant-on", non-volatile programming together with real time, unlimited reconfigurability found in SRAM-based FPGAs". It is difficult to envision many applications that require "unlimited reconfigurability" from a device with such limited densities. However, the company is targeting Xilinx's Spartan FPGAs with the 5000MX series and these SRAM-based parts can be reconfigured.

The use of the "system gates" to define the capacity of PLDs seems to be getting out of hand. It was first used by Xilinx to account for embedded memory and other embedded resources. The result has been highly inflated claims for the density of FPGAs. This exaggeration has been taken to a new level with the ispXPLD family.