As designers integrate multiple high-speed clock domains and complex intellectual property (IP) cores into large multi-million gate designs, they require new analysis and assignment tools to simplify the process of meeting their design's timing requirements. The Quartus II version 2.1 tool builds upon the LogicLock block-based design flow, introduced a year ago to increase designers' control over place-and-route, by offering improved integration between analysis and assignment tools. The emphasis on timing closure strengthens the Quartus II design software's support for Altera's new Stratix device family, which can support up to 40 unique clocks in a single device.

"Altera is taking a common sense approach to delivering the development tools required to support today's high-density FPGAs," said Rich Wawrzyniak, senior analyst, ASIC/SoC at Semico Research. "For a reasonable price, the Quartus II 2.1 design software delivers a compelling set of features allowing designers to quickly achieve timing closure in their most complex, multi-million gate designs."

Push-Button Netlist Optimizations
The new release of the software includes performance enhancing netlist optimizations in a push-button fashion. These new netlist optimization features can result in an up to 10-15 percent performance improvement over designs that do not use these optimizations. The Quartus II version 2.1 development software also includes improvements to the integrated synthesis tool. This new synthesis technology also includes language extractors licensed from Verific Design Automation Inc.

Timing Closure Interactive Floorplan
"In addition to Altera providing the best push-button FPGA performance available today, we are also giving designers control over the management of timing on complex SOPC designs," said Tim Southgate, vice president of software and tools marketing at Altera. "The Quartus II version 2.1 tool is the industry's best tool for extracting optimum performance from large FPGA designs with multiple high-speed clock domains."

Altera is also introducing the timing closure interactive floorplan, a powerful analysis tool that saves designers time and effort when interpreting the timing on the device. One of the most advanced innovations in the Quartus II version 2.1 software, the timing closure interactive floorplan provides designers with nine views of timing and placement within the device. Designers can view hierarchical timing relationships between various blocks in a design and edit, or create, timing and placement constraints within the design to optimize performance.

Path-Based Assignments
The Quartus II version 2.1 design software includes a new user-controlled optimization technique that can further reduce iterations in the place-and-route stage of the design flow. By using path-based assignments, the design engineer can easily make timing assignments to all points along a critical path identified by the timing analysis. Design engineers can reassign failing paths to a new LogicLock region and then recompile without having to go back and restructure their HDL code.

SOPC Builder Integration
An additional enhancement to the Quartus II design software is the inclusion of the SOPC Builder tool for system-level development. SOPC Builder is an automated system development tool that dramatically simplifies the task of creating high-performance SOPC designs. The tool automates the system definition and integration phases of SOPC development. Using SOPC Builder, designers can define a complete system, from hardware to software, within one tool and in a fraction of the time of traditional SOC design.

Spotlight on Verification
With the Quartus II version 2.1 tool, Altera will be extending this leadership to add support for formal verification and design rule checking tools. In concert with existing simulation tools, Altera designers can now use Conformal LEC from Verplex to verify the functional correctness of their designs. With support for design rule checkers such as Atrenta's Spyglass and Synopsys' LEDA, Altera designers can check for bugs in their designs before synthesis and simulation.

This latest edition of Quartus II extends the tool's capabilities for push-button operation and also for manual intervention for challenging performance requirements. Timing closure, a term borrowed from ASIC design flows, is one of the features emphasized in the new release. Timing closure generally means the process of iterating through the design until the timing requirements are met. This can be a frustrating and time-consuming process since changes made to fix one critical path can cause excessive delays in another path.

The timing closure process in Quartus II builds upon the LogicLock block-based design flow introduced about one year ago. This technique allows the designer to freeze the design of a specific block of logic and then be certain that its timing characteristics will not change as other parts of the design are modified. Timing closure for Altera's FPGAs is facilitated by taking data from the timing analysis stage and applying it during the early stages of the design flow.

This can be done automatically by the synthesis engine by employing post-synthesis optimizations that include re-synthesis, register retiming, and logic duplication. A second aspect of the timing closure process is user-driven and applies to manipulating the placement of the critical elements. Called the "timing closure interactive floorplan" by Altera, it allows designers to view hierarchical timing relationships between various blocks and to create timing and placement constraints.