The company also unveiled its FlashLock on-chip security feature, which adds another level of design security to the company's flash-based FPGA devices. In addition, 20 percent performance improvements have been made possible by Actel's design tools, Actel Designer software and Actel Libero integrated design environment. These security and performance improvements allow Actel to target a wider range of application-specific integrated circuit (ASIC) alternative applications. These include set-top boxes, video games, network and telecom line cards, industrial controls, wireless networking, medical and avionics.

"The industry's acceptance of Actel's flash-based offerings has exceededour expectations. Since its introduction earlier this year, the ProASIC Plus solution has won an unprecedented number of design wins in multiple market segments, making it the fastest ramping family in Actel's history," said John East, president and chief executive officer at Actel. "And now, with the new APA075 device, FlashLock security feature and 20 percent performance improvement derived from the Actel Designer and Actel Libero tools, we expect that a broader base of the design community will migrate to ProASIC Plus, especially in the cost-sensitive consumer arena."

The Design Security Advantage

As the complexity, capabilities and market share of FPGAs increase so does the need to secure the intellectual property implemented in FPGAs.Nonvolatile flash FPGAs, like Actel's ProASIC Plus family, offer levels ofdesign security beyond conventional SRAM-based FPGAs and ASIC solutions. Actel's ProASIC Plus FPGAs are user programmed with a key, ranging from 79 to 263 bits, that blocks external attempts to read or alter the configuration settings. Built from the ground up to offer enhanced design security, Actel has unveiled its on-chip security mechanism, called FlashLock, that enables designers to lock the design after programming to prevent unauthorized changes. The FlashLock feature can also be used to thwart common security problems faced by designers using conventional SRAM devices, including overbuilding, cloning, reverse engineering and denial of service.

Performance Improvements

Design benchmarks show that the Actel Designer R1-2002 software, announced in June 2002, and Actel Libero integrated design environment deliver an average of 20 percent better performance on ProASIC Plus designs in a variety of customer applications. This improvement was achieved through enhancements to the Quadratic Placer in the Actel Designer offering. Integrated into the Actel Libero integrated design environment or used as a standalone tool suite, the Actel Designer software includes place-and-route, timing analysis andmemory generation functionality to accelerate and automate the system design process without forcing the designer to relinquish control.

About ProASIC Plus

Actel's second-generation, reprogrammable, flash-based ProASIC Plus FPGA family delivers high performance with system speeds of up to 100MHz and allows designers to seamlessly interface between 3.3- and 2.5-V devices in a mixed-voltage environment. The family contains two advanced clock-conditioning blocks, each consisting of a phase-locked loop (PLL) core, delay lines and clock multiplier/dividers. Additionally, two high-speed LVPECL differential input pairs accommodate clock or data inputs.

In-system programmability (ISP) is supported through the IEEE standard 1149.1 JTAG interface. The single-chip, "live-at-power-up" APA075 device includes multiple PLLs and support for up to 27k bits of two-port embedded SRAM and 158 user-configurable I/Os.

Pricing and Availability

The new APA075 ProASIC Plus FPGA is one-half the size of the smallest part previously announced. The logic cells in the APA075 can be configured to create 3K registers compared to 6K registers for the APA150. In addition, the new device contains 27K bits of two-port embedded SRAM compared to 36K bits for the APA150. With some 6K logic cells, with two gates each, the programmable logic capacity of the new part is between 20K and 30K gates.

In addition to a 20% performance improvement resulting from the optimization of its tools, Actel also announced its FlashLock security feature. FlashLock uses a 79 to 263 bits key that blocks attempts to read or alter the configuration settings. The security feature already exists in the other ProASIC Plus devices and will be activated as production versions of the parts are delivered during 3Q02 and 4Q02.

The company makes the interesting point that FPGA security concerns have been growing as the capacity of the devices increases. This growth in capacity, plus a number of other factors, have led to the replacement of ASIC-centric board designs with ones where the FPGA is the primary element. The ASIC-centric boards were inherently secure since copying the ASIC was difficult and expensive. The FPGAs in the FPGA-centric boards contain a great deal of company and third-party IP. The configuration data for SRAM-based FPGAs is relatively easy to copy since it must be loaded into the device at startup.

Lattice Semiconductor and Xilinx have also paid some attention to the design security problem. Xilinx, in its Virtex-II devices, codes the configuration bit stream in accordance with a triple-DES algorithm. The key for the algorithm is stored in the FPGA. This creates the need for placing a battery on the board since SRAM is the only memory in the device.

Lattice's recently introduced ispXPGA has on-chip non-volatile EEPROM to retain the configuration data. A single security bit is used to secure the data. Single-bit security approaches are not impossible to circumvent.

While telecommunication and networking applications will continue to lead the PLD market, it is becoming increasingly clear that this sector's domination has and will continue to decline. Design security will be an increasing concern as consumer equipment becomes a larger part of the FPGA market. Misappropriation of designs is symptomatic of the consumer electronics industry.

Actel is very pleased with the rate of design wins for the ProASIC Plus devices and expects that the family will be a significant revenue source in 2003. However, there are two shortcomings that will limit the acceptance of the ProASIC Plus devices. These are its relatively low speed and the lack of I/Os that can be set for the different signaling standards.

The devices do have a pair of PECL inputs, primarily for clock signals. The I/O deficiency won't be eliminated until the middle of 2003 when the 0.13-micron versions become available. Actel has announced that it will use Infineon as the fab for these parts, which will be made using the company's standard flash process.