Mentor Graphics Corporation and Xilinx, Inc. today announcedan agreement to develop a customized extension to the market-leadingSeamless co-verification environment, optimized to the needs of designers using the Xilinx Virtex-II Pro Platform FPGA devices. Under the terms of this agreement Mentor Graphics and Xilinx will tailor a co-verification solution to the requirements of designers embedding thePowerPC 405 Core into Virtex-II Pro devices. The collaboration result willbe a co-verification solution for FPGAs that is more tightly integrated than any previously announced solution, significantly easing the adoption of the technology into the Xilinx design flows.The Seamless Virtex-II Pro solution builds upon the existing Seamlessco-verification environment and the production-proven, general-purposePowerPC 405 Seamless processor support package (PSP). Encapsulatingknowledge of the Virtex-II Pro devices within this co-verification solutionsignificantly reduces integration time, enabling designers to be moreproductive in a shorter amount of time.

"Platform FPGAs with powerful embedded cores afford designers a level ofintegration not possible with previous generations of programmable devices," said Serge Leef, general manager of the System-on-Chip Verification Division at Mentor Graphics. "As designers adopt this methodology they will face some of the same verification challenges associated with ASIC/SoC design. Seamless has proven time and again a valuable solution in simplifying and speeding this process."

Programmable Systems Deliver Rich Feature Set with Integrated Processor Performance

Embedding processor cores into programmable devices increases the complexity of verifying such devices. The Seamless Virtex-II Pro solution addresses these issues and simplifies the process of designing with programmable systems even easier by providing designers with a virtual prototype of the platform FPGA weeks or months ahead of the time when the first physical prototypes can be programmed.Critical to the success of verifying a complex embedded device is theability to control and visualize the operation of the system during thedebug phase. Seamless co-verification encompasses the logic simulation and software debug tools already in use in system design and verification. Access to these tools within a virtual environment gives a level of controland observability not achievable with physical devices, not only forpre-silicon debug, but also for improved visibility when analyzing problems encountered on physical prototypes.

"Xilinx is committed to providing our customers with a comprehensive debug and verification strategy to adequately address the increased system level complexity of Virtex-II Pro based designs," said Rich Sevcik, senior vice president of FPGA products at Xilinx. "As part of our overall strategy we are pleased to work with Mentor in supporting Seamless, a proven ASIC strength co-verification tool to our customers".

The Platform FPGA will be part of a complex system that will also require verification. Often this system will contain other processors and digitalsignal processors (DSPs). Seamless offers the most comprehensive range of processor models with support for all popular embedded architectures, making Seamless the solution for both the system and device verification.

Pricing and Availability

Hardware/software co-design and co-verification are really two different problems. Co-design is a system-level chore that tends to be an iterative process. A hardware/software partition is made, evaluated, and then modified to suit the designer's goals. Hardware/software co-verification is the process of evaluating and debugging the design.

In ASIC or SoC design, this process is typically done by using EDA tools that operate on a virtual prototype of the design. Processor/FPGA designs give the engineer the option of evaluating an actual prototype. However, finding and evaluating errors in a hardware-based prototype of a complex hardware/software system can be difficult and time consuming. The use of tools such as Mentor's Seamless in conjunction with traditional logic simulators and software development environments can be a major aid in optimizing and debugging a design.

Xilinx has been a bit slow in bringing hardware/software co-verification capability to its Virtex-II Pro design environment. Atmel had an integrated version of Seamless in its toolset when it introduced the FPSLIC family of integrated processor/FPGA devices.

Xilinx, at about the same time that it announced its work with Mentor on Seamless, introduced a lower cost hardware/software co-verification tool in conjunction with Endeavor Intertech. The two companies claim that Endeavor's CoSimple provides virtually the same co-verification capabilities of existing co-verification environments at a price of under $10,000.