"By offering a C-code based design flow, Altera puts advanced FPGA-based reconfigurable DSP technology into the hands of DSP designers without forcing them to learn hardware description language." said Will Strauss of DSP industry watcher Forward Concepts. "For many DSP designers, the lack of a standard C-code based design flow has been a barrier to using FPGAs in a broad range of lower-performance, mainstream DSP applications." According to Forward Concepts, the market for DSP devices programmable in a C-code environment is over $5.8 billion this year.

In addition to the new design flow, Altera's Code:DSP initiative includes a development platform based on the industry's leading Stratix FPGA family as well as comprehensive support programs. By delivering comprehensive set of DSP solutions, Altera is able to take advantage of opportunities in the DSP market that reach beyond the wireless infrastructure applications that are a traditional stronghold for FPGAs.

Design Flow Provides Advantages of Both Software and Hardware Development

In Altera's DSP design flow based on C code, the designer writes C code that executes on the Nios embedded processor. For optimal implementation of DSP algorithms, the designer can use custom DSP instructions developed using MATLAB and Simulink tools. These custom instructions are integrated into the reconfigurable DSP design using Altera's DSP Builder and SOPC Builder tools. This flow is quicker and easier for DSP designers when compared to the traditional hardware description language-based design flows previously offered by FPGA vendors.

"By leveraging our embedded processor leadership with our comprehensive portfolio of DSP algorithm IP, we can offer DSP designers a standard C code-based design flow, and a strong incentive to begin using it," stated Jordan Plofsky, senior vice president of applications business groups at Altera. "This offering positions Altera as the broadest-based DSP market supplier among PLD vendors, underscoring our intention to be one of the top suppliers to this market."

Stratix-Based Solutions Underpin Code:DSP Initiative

Stratix devices are the industry's first FPGAs to offer embedded DSP blocks, which include multiply-and-accumulate (MAC) structures that efficiently implement high-performance DSP functions such as FIR filters. In addition, the DSP capabilities of Stratix FPGAs can be extended with the use of an Altera patented technique for building "soft multipliers" using the Tri-Matrix memory structures, allowing DSP designers to balance device resource utilization to achieve maximum optimization. This technique increases the number of available multipliers up to 500%, which enables Stratix FPGAs to deliver DSP performance unmatched by any other available FPGA.

Today, DSP designers can take advantage of Altera's DSP algorithm IP MegaCores, which are optimized for the Stratix FPGA architecture to take advantage of the device's embedded DSP blocks. Using Altera's DSP IP MegaCores, designers can build systems using fully customized finite impulse response (FIR) filters, fast-fourier transforms (FFTs), Reed-Solomon encoders/decoders, numerically-controlled oscillators, and Viterbi encoders/decoders. Evaluation of these building blocks is free of charge via the OpenCore flow, which is available to all users of Altera's Quartus II 2.1 software.

Comprehensive Support For DSP Designers

Altera's Code:DSP initiative includes a complete support program for customers developing FPGA-based reconfigurable DSP designs. First, Altera has created a DSP chapter of its Certified Design Center (CDC) and Altera Consulting Alliance Program (ACAP) to assist customers with their designs. Partner organizations all over the world, expert on Altera products, are available to provide localized DSP application expertise. Charter members of the DSP chapter include: Adaptive Micro-Ware, Colorado Electronic Product Design, Digital Design Corporation, Nuvation, Plexus Technology Group, Synopsys Professional Services, Vanteon, Alcahest, El Camino, Plextek, Telecom Italia labs, and Dexcel Electronics Designs.

Second, Altera has launched a new web-based DSP Solutions Center to provide comprehensive, up-to-date information and resources for DSP designers who want to reap the benefits of programmable logic. Finally, Altera offers training courses targeted at DSP designers who want to get up to speed quickly on the latest tips and techniques for creating efficient, high-performance DSP designs.

Altera is launching Code:DSP in an effort to expand the role of its FPGAs in the DSP market beyond the high-performance algorithm acceleration segment. FPGA use in DSP applications currently account for only 2% of a $12 billion market - primarily in cellular base stations for algorithm acceleration. Many DSP applications do not require that level of performance and Altera intends to pursue these with its Code:DSP program.

The four new elements in this initiative are a C-based DSP design flow, soft multipliers that can be implemented using the embedded memory blocks in Stratix, a Stratix-based DSP development kit, and a DSP chapter of Altera's design and consulting associates to provide localized DSP application expertise.

The key to attracting some of the lower-performance DSP applications lies in the use of Altera's NIOS soft 32-bit RISC processor core in conjunction with the newly developed C-based design flow, Stratix devices, and DSP Builder. NIOS has been an unqualified success and Altera now claims more than 6,000 registered users for the processor that was introduced just two years ago.

Improvements in the processor core and the company's FPGAs have resulted in speeds of up to 125 MHz. Features that makes NIOS attractive for DSP applications are its ability to execute custom instructions and its DSP Builder interface.

Most DSP processors run a combination of control instructions and DSP-related ones. The DSP code usually includes both simple and complex recursive algorithms. It is the recursive algorithms that consume most the DSP processing cycles. TI has recognized the need to execute both control and signal processing instructions with the introduction of its OMAP5910 device. This part integrates a TMS320C55x DSP core and an ARM925 RISC core on a single chip.

Altera's goal is to use the NIOS processor core for both the control and DSP instructions, completely eliminating the need for a separate DSP device. Special instructions are devised for those simple signal processing tasks and complex recursive algorithms that are accelerated in a portion of the same Stratix FPGA that contains the NIOS processor. The company's new C-based design flow from MATLAB/Simulink is the key to implementing this vision.

The design flow allows the DSP designer to develop, refine, and validate the required algorithms in the familiar MATLAB/Simulink environment. These results are then encapsulated in the processor's C code, either as a special instruction or as a call to a hardware-accelerated function. The hardware portion of the accelerated function must still be developed in the conventional manner using Altera's DSP Builder, DSP IP cores, and Quartus tools.

According to the company, the soft multipliers are ideal for multiplication-intensive applications such as image processing and 3G wireless base stations. When combined with the 112 multipliers from the DSP blocks, the largest Stratix device provides up to 612 multipliers that can be used for implementing distributed arithmetic computations as well as multi-channel applications such as echo cancellation, multi-user detection, and antenna beam-forming. Another advantage of the soft multipliers is that they can be configured to execute other than the fixed 18x18 multiplications in the embedded DSP blocks.

Altera's DSP Development Kit, which sells for $1995 for the starter version, has been upgraded to include the Stratix EP1S25F780 FPGA, a 2-channel 12-bit, 125-MSPS A/D, and a 2-channel 14-bit, 165-MSPS D/A. The kit now supports NIOS and DSP hardware acceleration.