Xilinx is leveraging its proven market and technology leadership in logic design to stake out a leadership position in programmable system design, a rapidly growing market that's projected to more than double to nearly $6 B in 2004 from $2.6B in 2001, with FPGA and embedded design dominating the growth. As the fifth largest ASIC/PLD company worldwide with $1.02 B in revenues in FY2002, according to Dataquest, Xilinx commands 50 percent market segment share in the PLD industry -- larger than all other competitors combined.

"Xilinx is making a significant contribution to the EDA tools industry. For example, IBM will be using future versions of these tools for its next generation ASICs including the Xilinx/IBM hybrid chip. And, with an installed base of more than 150,000 design seats, Xilinx EDA tools are widely regarded as part of the de facto standard methodology for programmable logic design," said Cary Snyder, noted industry expert at PC2 Consulting and former industry analyst at Micro Design Resources.

"Just six months ago, Xilinx enabled a new era of system design using a programmable platform, with hardware features such as embedded processors, gigabit serial I/O, and advanced bus structures," said Rich Sevcik, senior vice president of FPGA Products at Xilinx. "To fully exploit the Virtex-II Pro programmable system platform, Xilinx, with our EDA, embedded software and co-design partners, is building a complete, integrated design flow that merges mature industry standard hardware and software flows with innovative hardware/software co-design and verification technology."

ISE 5.1i delivers "ASIC-strength" tools to exploit Virtex-II Pro series silicon performance

With ISE 5.1i, Xilinx is delivering "ASIC-strength" design tools to exploit the power of Virtex-II Pro silicon, ranging in device densities from 40,000 to more than eight million system gates. Designers will benefit from a 2X improvement in compile times (an increase from 100,000 to 200,000 gate/min) and a 40 percent gain in device speeds over last year's software release. In addition, they'll get early access to the most advanced device architectures for Xilinx FPGA products, such as Virtex-II Pro devices, several months before first silicon. ISE 5.1i allows logic designers to finish designs faster with less risk using key new features, such as:

-- True incremental design to enable more turns per day
-- Advanced Pinout and Area Constraints Editor (PACE) management tool to
simplify the specification of device IO and pin assignment
-- Architecture wizards to simplify the design of the industry's most advanced multi-gigabit serial transceivers, and on-chip digital clock management capabilities
-- Macro Builder, to enable design reuse by capturing physical IP implementation and preserving placement information

Building on excellence in programmable logic design to lead in embedded and system design

With the advent of programmable systems on a single chip (by combining processors, high-speed I/Os, memory, programmable logic and other system IP, all manufactured with the latest manufacturing process technology), FPGA usage is on the rise for ultra-high bandwidth system-on-a chip (SOC) designs as an alternative to ASICs. Previously the exclusive domain of custom ASICs, programmable system designs are inherently more flexible, with lower non-recurring engineering (NRE) costs.

In order for engineers (i.e., system architects, embedded software designers and hardware designers) to effectively manage design complexity, a new design paradigm must include: high-level language support to capture design functionality; profiling and characterization to explore design trade-offs; debug and verification tools to ensure correctness; and compilers and optimizations for production implementation.

According to Sevcik, "The 'ultimate' programmable system design methodology from Xilinx will be based upon on-demand architectural synthesis, allowing designers to define system functionality at a high level of abstraction, then debug, synthesize and verify a range of architecture implementations that meet system specifications. Just as importantly, it will accommodate design exploration for determining the optimal hardware implementation, and changes in hardware/software partitioning to achieve optimal cost/performance, without having to modify the source specification."

Already, Xilinx has announced the System Generator for DSP, which enables designers to model a DSP system and generate an FPGA implementation using The MathWorks Simulink and MATLAB tools. The company has also announced partnerships with Synplicity for physical synthesis, Wind River Systems for embedded design support, Monta Vista for embedded Linux support, Mentor Graphics for co-verification support, as well as leading EDA partner support for architectural synthesis tool joint development. Throughout the remainder of 2002, Xilinx will roll out a series of embedded and system-level ISE 5.1i family and EDA partner design tools that enable on-demand architectural synthesis and flexible hardware/software partitioning.

Bridging the system design gap with programmable logic

With today's announcement of ISE 5.1i, Xilinx is delivering "ASIC-strength" design tools aimed at bridging the system design gap with programmable logic. Because Xilinx programmable system solutions are built on proven silicon, designers can focus on system design and verification rather than silicon testability to significantly minimize design time and costs. Additionally, designing Virtex-II Pro FPGAs with ISE gives users the tools to take advantage of advanced hardware features.

Incremental Design:

Incremental Design enables change without risk by reducing the impact of late-cycle design changes. Once place-and-route is completed, this new feature of ISE 5.1i makes it possible to lock down placement and routing to preserve performance of areas of a design that haven't been modified. It also accelerates compilation time by ensuring that only the area affected by a design change is re-implemented and preserving the layout of the remainder of the design. Overall timing closure is reached faster, and less time is spent in the design flow. The industry's leading EDA suppliers provide advanced synthesis technology that supports ISE 5.1i incremental design technology.

HDL coding-style checkers from Atrenta and Synopsys allow customers to verify the programmable design coding style for optimized performance with Xilinx devices. Atrenta's SpyGlass now supports ISE 5.1i by offering predictive HDL analysis for Xilinx's FPGAs. Synopsys LEDA ruleset has been expanded to double the number of design rules available for targeting Xilinx FPGAs including Virtex-II and Virtex-II Pro series. Xilinx's ISE along with the HDL coding-style checkers from our partners will increase your productivity and reduce your time to the most optimized design.

Pinout & Area Constraint Editor (PACE):

To eliminate productivity bottlenecks inherent in a complex logic design flow, PACE simplifies pin management and area with: drag-and-drop I/O assignment, color-coded busses and groups, automatic differential IO pairing, automatic voltage banking, and a wide variety of pin design rule checks. PACE also offers sophisticated floorplanning tools, including design hierarchy retention, design rule-driven floorplanning, and built-in area checking.

Architecture wizards:

To ensure that engineers get optimal use of Virtex-II and Virtex-II Pro FPGAs, architectural wizards simplify access to advanced features. For instance, the Digital Clock Managers (DCM) wizard and RocketIO multi-gigabit transceivers (MGT) wizards let the user graphically set DCM and MGT functions through dialog boxes available in the ISE Project Navigator. ISE then writes editable source code directly into the HDL source file to set and control these advanced capabilities. The Architecture Wizards enable correct-by-construction HDL code, alleviating the need to learn all of the programming attributes required to configure these powerful flexible device features, thereby speeding the design cycle. In a related announcement, Xilinx and Cadence delivered a kit for designing with MGTs in Virtex-II Pro devices.

Macro Builder:

Accessible from within the ISE Floorplanner, Macro Builder enables design reuse, making it possible for customers and IP vendors to capture physical implementations of internally-developed IP; preserve placement information for timing-critical blocks; and ensure repeatable high-performance in future designs. Changes in other parts of a design do not affect macro performance, further supporting change without risk.

In related news, Xilinx announced it would begin shipping the latest release of its popular ChipScope Pro tools, the most comprehensive set of on-chip debug and verification tools on the market today.

Price, platform and availability

I continue to be amazed by ongoing improvements being made in the design tools developed by the PLD device producers. Each major release from these companies produces a 10% to 15% increase in device performance and a significant decrease in compile times. Compile times of this release of ISE are twice as fast as the previous release - ISE 4.li.

The new ISE 5.li design tools, when combined with Virtex-II Pro devices, are said to yield 40% higher speeds than the results attained one year ago with Virtex-II. The claim from Xilinx is that "high performance system designers can now achieve unprecedented clock rates of over 400 MHz, and the fastest logic performance available in a programmable solution."

Xilinx also announced that it will begin shipping ISE ChipScope Pro 5.1i next month. This version of the company's design debugging tool includes IBM CoreConnect integrated bus analyzer (IBA) cores, core insertion tools, and an analyzer interface for on-chip capture of data related to on-chip peripheral bus transactions. CoreConnect is the on-chip peripheral bus that is used in conjunction with IBM PowerPC processors embedded in the Virtex-II Pro family of FPGAs.

ChipScope Pro extends the logic analyzer technology contained in ChipScope ILA (integrated logic analyzer) to Virtex-II Pro. These transactions are captured in internal BlockRAM and accessed via a JTAG port. The new debugging tool includes the Core Inserter flow, which enables designers to insert ChipScope Pro cores into the design netlist. According to the company, the ChipScope Pro Inserter flow offers the flexibility to add and remove debug cores at any time throughout the design cycle.

The company says that it "is building a complete, integrated design flow that merges mature industry standard hardware and software flows with innovative hardware/software co-design and verification technology." The two elements in this effort are a high-level language (HLL), such as C/C++, for design entry and on-demand architectural synthesis.