"Cyclone devices are the first FPGAs that offer the right density, features, and performance to rival ASICs for high-volume applications," said Peter Voldstad, senior design engineer, Polycom Video Conferencing Systems. "At these prices, we don't have to look at ASICs anymore."

Low Cost by Design
Breaking with the industry's tradition of reusing an existing architecture or re-branding an existing product to create a low-cost FPGA, Altera built the Cyclone device family from the ground up, using the same product-definition process that successfully yielded the Stratix device family. Collaborating closely with more than a hundred customers around the world to define the new product's price threshold, features, density, and performance requirements, Cyclone devices include a focused set of features and are three times the density of previous low-cost FPGAs. More significantly, Cyclone devices have a 60 percent die-size reduction over previous architectures.

John Daane, Altera's president and CEO stated, "Our goal is to give our customers a competitive edge -- which to us means FPGAs targeted to specific applications. To achieve that, it is vital that they be involved in our product definition process," he stressed. "As a result, Cyclone devices have the right capabilities that enable designers of high-volume systems to consistently reap the benefits of programmable logic from prototyping into very high-volume production."

Advantage Over ASICs
FPGAs have historically found their sweet spot in high-bandwidth, high- performance applications where end products cost thousands of dollars. Designers of high-volume applications have traditionally turned to ASICs due to their cost effectiveness. However, the spiraling economics of designing ASICs -- the high-cost of non-recurring engineering (NRE) charges and the uncertainty of end-market success -- are rapidly favoring programmable logic. Long known for their time-to-market benefits, FPGAs have the advantage of being off-the-shelf customizable products that require no up-front costs and no minimum-order quantities.

"Demand in many markets is still in the process of re-balancing itself. At the same time, design cycle times for complex ASICs are not becoming more manageable. A low-cost FPGA device with relatively high-performance and small die size could not have been introduced at a more opportune time," said Richard Wawrzyniak, senior analyst at Semico Research Corporation. "Designers now have a new option that brings a programmable logic solution further within their cost and performance targets for cost-sensitive designs. Cyclone devices are going to change the way people look at programmable logic and what they can do with an FPGA."

Embedded Processor for Less Than $2.00
A single Cyclone device with multiple Nios embedded processors can achieve designers' goal of reducing costs without sacrificing system performance. Consuming less than half the LEs of Altera's smallest density Cyclone device, which costs $4.00, the effective price for Altera's Nios processor is less than $2.00. A 32-bit Nios microprocessor and peripherals configuration consumes less than 1,400 LEs and delivers 50 Dhrystone MIPS (D- MIPS). Tim Colleran, vice president of product marketing at Altera said, "Cyclone devices, combined with our Nios processor, are clearly targeted to extend the system-on-a-programmable-chip (SOPC) technology to a whole new customer base that drives much higher-volume applications."

Cyclone Device Features

-- Density and Memory: Cyclone device densities range from 2,910 to 20,060 logic elements (240,000 logic gates and over 1 million system gates) and up to 288 Kbits of RAM.

-- Dedicated Memory Interface Circuitry: Cyclone devices are optimized to seamlessly communicate with double data rate (DDR) SDRAM and FCRAM devices as well as single data rate (SDR) SDRAM devices at up to 266 megabits per second (Mbps).

-- I/O Standards: Cyclone devices support a variety of single-ended I/O standards for off-chip data transmission, including LVTLL, LVCMOS, PCI, SSTL-2, and SSTL-3. For designers requiring faster data rates and more robust signal transmission capabilities, Cyclone devices feature up to 129 low voltage differential signaling (LVDS) compatible channels, each capable of performing at up to 311-Mbps.

-- Configuration: Altera's new serial configuration device family is designed for the lowest possible cost. Representing an additional cost that is less than 10 percent of the price of the FPGA itself, these devices further extend the price advantage of Cyclone devices compared to other low-cost programmable products.

Pricing and Availability
The combination of Cyclone devices, Altera's extensive intellectual property (IP) portfolio, the free Quartus II Web Edition design software, the Nios soft-core embedded processor, and Altera's new low-cost serial configuration devices delivers the lowest-cost, complete SOPC solution in the industry.

The Cyclone EP1C20 device will be available in Q1 2003. All family members will be in full production in the first half of 2003. Software support is available immediately with the Quartus II version 2.1 (service pack 1) design software. For customers that do not have an active subscription to Altera's tool suite, the Quartus II Web Edition software is available for free from Altera's web site, giving customers free access to the entire Cyclone device family.

EP1C3 - (1) $7.00 - (2) $4.00
EP1C6 - (1) $17.00 - (2) $8.95
EP1C12 - (1) $35.00 - (2) $25.00
EP1C20 - (1) $60.00 - (2) $40.00

This time Altera seems serious about pursuing low cost FPGA applications. In the past, the company made some half-hearted attempts in this direction with its FLEX 6000 and ACEX product introductions. Cyclone is a coherent family with four members ranging in capacity from 2.9K to 20K logic elements. The FPGAs will be made by TSMC using its leading-edge 0.13-micron, all copper, process.

Altera is targeting those markets with quantity requirements of 100K to 5 million units. Products incorporating Cyclone devices will have a typical end-user price that ranges from $200 to $1000. Altera will find that it is not alone in pursuing this market segment. Actel and Xilinx have been active in providing low-cost FPGAs for these same applications for some time.

Altera's claim that Cyclone is "half the cost of competing low-cost FPGAs" should be taken with a large grain of salt. It is comparing the price that it expects to reach in about two years with the price for a product that has been shipping for nearly one year. It is very likely that others will be able to reach a similar price point at that time - or even before. Xilinx, for one, expects to deliver the fifth generation of Spartan early next year. It is likely that the new Spartan family will be built using a process similar to the one being used for Cyclone.

Xilinx has just announced the shipment of the 40 millionth low-cost Spartan FPGA. This five year old family is now in its fourth generation with the latest devices, the Spartan-IIE, being produced using a hybrid 0.18/0.15-micron process. The company claims that Spartan has produced nearly $500 million in cumulative revenues and that shipments of these families now account for 13% of sales.

Altera's claim that it is opening new markets for FPGAs with Cyclone does not really hold water. It is actually pursuing the same markets that Xilinx and Actel have been serving for some time. With the exception of capacity and the ratio of user I/Os and embedded memory to logic elements, Cyclone's features are very similar to those already present in Spartan-IIE.

The Spartan-IIE series has five members with capacities ranging from 1.7K to 6.9K logic cells. This can be compared with a much broader range of 2.9K to 20K logic elements for the four parts in the Cyclone family. The higher capacity of the Cyclone parts will give Altera an advantage over Spartan-IIE in a number of applications. The next generation of Spartan, however, could eliminate this advantage.

Cyclone has more embedded memory and less user I/Os that Spartan-IIE for a comparable capacity part. For example, compare the Cyclone EP1C6 and the Spartan XC2S300E, which have a similar number of LUTs. The Cyclone part has about 50% more embedded memory than the Spartan one, but the Spartan device has nearly 80% more user I/Os than Cyclone. Altera has sacrificed I/Os to minimize die size. These architectural features, rather than price, will likely prove to be the real differentiator between the two families in the future.

Altera has designed Cyclone so that all of the family members are pad limited. This means that die size is determined by the number, size, and spacing of the I/O pads and not the logic circuitry. The die size of a gate array or cell-based ASIC with the same number of I/Os will not be any smaller and should cost about the same. A cell-based ASIC would be designed to meet a specific set of user requirements and will usually have fewer I/Os than a general-purpose FPGA, giving it a small cost advantage. However, it is becoming increasingly clear that FPGAs are effective competition for both gate arrays and small cell-based ASICs.