By combining QuickLogic's MIPs-based programmable System-on-Chip (SoC) with PACT's XPP re-configurable coprocessor, the companies expect to offer a platform that embeds a CPU, programmable logic and re-configurable DSP capability for applications that require high-performance, high throughput and low power. The agreement is co-signed by MIPS Technologies, which will provide the necessary information to define the coupling of the MIPS hard cores to the XPP array and QuickLogic's secure ViaLink programmable QuickMIPS architecture.

"Developing a platform that utilizes these unique technologies represents the next significant milestone in our ESP development for the QuickMIPS product line," said John Birkner, VP and co-founder of QuickLogic. "Using PACT's massively parallel, XPP cores as an algorithmic co-processor in tandem with the flexible MIPS RISC CPU gives designers a hardware- and software-programmable solution that has thus far been reserved for ASICs or dedicated DSPs."

"A closely-coupled architecture between QuickLogic, MIPS Technologies and PACT combines to give a turbo-charged effect," said Tom Hart, President and CEO of QuickLogic. "Basically, it would provide the benefits of software and hardware programmability on a flexible platform, significantly increasing performance and reducing power over today's DSP or microcontroller-based solutions."

PACT, a fabless German company, introduced its eXtreme Processing Platform (XPP) in October 2000 after a four-year development effort. The company, at that time, demonstrated a proof-of-concept chip that was made using a 0.25-micron process. The demonstration device, the XPU128, contained 128 32-bit arithmetic processor cores and, according to the company, can run 51 billion operations per second when operated at 100 MHz. This is claimed to be equivalent to 70 Pentium 4 processors running at 1 GHz.

PACT intends to license its parallel and reconfigurable IP cores to other semiconductor companies for use in high-performance signal processing applications. The company claims to be in licensing discussions with Agere, Altera, Infineon, LSI Logic, Motorola, STMicroelectronics, and Texas Instruments. PACT, so far, has recruited six design services organizations, including Synopsys and Tality, to help potential users integrate the XPP core into ASIC designs.

The chip consists of an array of what the company calls Processing Array Elements (PAEs). These PAEs are not identical. For example, ALU-based PAEs can have cores with word sizes of 16 or 32 bits and DSP opcodes such as one clock multiply accumulate. Other ALU-based PAEs can be used for application specific functions or floating point support. RAM-based PAEs contains a RAM cell that can be used in number of different modes. Each PAE also contains the configuration logic, horizontal, and vertical high bandwidth routing channels.

According to the company, an array of any size can be designed on a basic grid, due to the transparent interfaces and the identical footprint of PAEs of different functionality. A number of I/O elements that support data streams or access external RAMs can be located at the edges of the array.

It will be a long time, if ever, before a single chip integrating the QuickLogic QuickMIPS device and a PACT XPP core is produced. The initial approach will be to produce a board containing the QuickMIPS chip and the existing XPP demonstration device. The two companies will then work with potential customers to develop and implement specific applications. A single chip device will be produced if sufficient interest is developed.