Luminance technology includes the patented modular array architecture, industry standard third-party tools, a rich portfolio of Lightspeed and third-party intellectual property (IP) and industry-renowned customer support.

"We designed our modular array ASIC approach to allow more design teams effective access to deep submicron technologies," said Dave Holt, President and CEO of Lightspeed. "Until Luminance, companies have been saddled with two expensive choices: slower, power-hungry FPGA prototyping solutions that are extremely expensive in volume production; or standard-cell ASICs with the inherent problems of development times up to 18 months and high NREs.We've solved these problems with a solution that delivers the fastest time to market at blazing fast speeds."

Utilizing a two metal mask, one via mask customization in conjunction with TSMC's 0.13µ 8 layer copper, high performance CMOS process technology, Lightspeed's newest Modular Array ASIC will provide up to 10 million usable ASIC gates and up to five million bits of embedded dual-port RAM. The high-density architecture includes embedded PLLs, SRAMs and configurable I/O cells. These elements are optimized for maximum array efficiency that delivers an unparalleled degree of versatility for designing high-performance systems across a wide range of applications.

Luminance architecture excels in advanced I/O systems including the emerging standards such as SPI 4.2 and HyperTransport. Selected family members will have on-chip 622 Mb/s-3.2Gb/s SERDES. All family members are designed to support high performance flip chip packaging.

The underlying AutoTest structure ensures that 100% stuck-at-fault detection is accomplished without any design-for-test rules, user intervention or test overhead implications for the logic designer.

Lightspeed's innovative AutoBIST technology enables the detection of path delay faults. Additionally, SiliconView allows in-system access to all chip states to assist with initial system bring-up and debug, allowing the designer to set states that are difficult to create through normal user-modes.

Lightspeed is continuing its efforts to bring the benefits of small feature size processes to the designer without the costs associated with a full cell-based ASIC design effort. The company is positioning its Modular Array families as FPGA alternatives, particularly targeting Xilinx devices. Like Virtex-II, I/Os in the new family can be set for a large number of different signaling standards, have built-in JTAG, and support the digitally controlled impedance feature. Double data rate registers to support high-speed external RAM are included in the I/O cells.

The key benefit of Lightspeed's approach is that its device can be customized to a specific design with only a few layers of the metal. Needing only two metal layers, the Lightspeed devices not only dramatically reduce the NRE mask charge, which can reach $1 million for a 0.13-micron process, it also reduces the time required to produce prototypes or to move to production. This is because nearly completed parts can be inventoried at the wafer level and quickly customized.

A number of other companies, including AMI, Chip Express, eASIC, and Fujitsu Microelectronics, also offer low-NRE devices that can be customized with several metal layers. The HardCopy devices from Altera fit in this category, but are only capable of converting designs for Altera's FPGAs.

NEC Electronics has introduced two families of low-NRE ASICs. The first family is its Instant Silicon Solution Platforms (ISSPs) that is being produced using the company's 0.13µ UX4 process. This series contains three members with rated logic capacities of 227K, 530K, and 1,109K gates. Each of the basic cells contains multiplexer-based logic and a register. The largest part in the series contains some 60K registers.

NEC estimates that the density of its ISSPs will be one-third to one-quarter of a cell-based ASIC. It expects prices to be about $35 each for the 200K part and about $150 for the largest device in the family. Even though NEC is targeting designs with volumes between a few thousand and 100,000 units, it will be economical to replace high-density, multi-thousand dollar FPGA designs for volumes of several hundred units.

NEC's second ISSP family, SoCLite (PDF) contains an embedded ARM7TDMI processor, 2 Kbytes of boot ROM, 8 Kbytes of SRAM, a variety of peripherals, and 190K gates for user defined logic. The company plans on expanding the ISSP line in early 2003 with two new families. One will include an embedded processor core, and the other will include Gbits/s I/Os. The I/Os in the current ISSP family can be mask-programmed for 3.3 V or 2.5 V, HSTL, SSTL, or 622 Mbits/s LVDS signals.

LSI Logic has also moved in the low-NRE ASIC direction with its recently announced RapidChip platform. The company's approach is to provide a silicon platform with a substantial amount of embedded resources and a gate array section, with a three to eight million gate capacity, for other IP and customer logic. The gate array section of the device can be customized using four metal layers.

LSI intends to introduce a number of different platforms for communications, storage, and consumer applications. The embedded resources will match the application and will usually include a RISC and /or DSP processors, three to ten Mbits of memory blocks, PLLs, and metal configurable I/Os that include high-speed differential pairs. Other embedded elements could include interface circuitry, SERDES, multipliers, MACs, FIFOs, multi-ported SRAM, etc.

Lightspeed's new Luminance family will cover the 250K to 10,000K logic gate range. The amount of embedded dual-port SRAM will vary from 540K to 5,000K bits.

Lightspeed claims that an important test-related distinction must be made between competing low-NRE ASIC solutions. The critical difference is the test strategy taken by the different vendors. Most low-NRE ASIC vendors require the customer to employ standard DFT rules to support manufacturing test.