"Lattice continues to deliver innovative solutions for high performance system-level design," said Stan Kopec, vice president of corporate marketing at Lattice. "The ORT82G5 is our latest generation backplane FPSC, following our successful ORT4622 and ORT8850 devices. These tests verify the superior speed and flexibility of our solution. Backplane applications, especially XAUI and Fibre-Channel, are a perfect fit for the ORT82G5. The eight independent, full-duplex serializer-deserializer (SERDES) cores are best-in-class with 3.7 Gbits/sec bandwidth, and the programmable logic will allow system designers to interface to virtually any processor or framer," he added.

Lattice's FPSC devices are high-performance programmable devices that combine optimized embedded core functions together with flexible, general-purpose FPGA logic. In addition to its eight SERDES cores and 400K ORCA FPGA gates, the ORT82G5 includes embedded XAUI and Fibre-Channel state machines, bypassable 8B/10B encoding/decoding support plus multi-channel alignment capability without using any FPGA gates. At 225mW per channel, the device offers designers the highest available bandwidth at very low power.

"By optimizing the device's programmable amplitude and pre-emphasis settings, minimum power consumption can be realized with the ORT82G5 while maintaining the signal integrity needed for error-free operation. This is the kind of tangible benefit Lattice's programmable approach offers system designers as they develop advanced communications systems," added Kopec. The device also features 372 programmable user I/Os supporting a variety of advanced interface standards including HSTL, SSTL, GTL+ and others to facilitate easy interfacing. Designers can use the ORT82G5 to aggregate disparate parallel I/O into high-speed serial streams. For example, designers can build a 20 Gbits/sec bridge for 10 Gbits/sec Ethernet; the high-speed SERDES interfaces contain dual-XAUI interfaces with configurable back-end interfaces such as XGMII implemented on the FPGA side. The ORT82G5 can also be used to provide a full 10 Gbits/sec backplane data connection with protection between a line card and switch fabric.

Lattice has demonstrated the ORT82G5 in its own lab using a Tyco HM-Zd test setup. The ORT82G5 can drive 2^7-1 PRBS data over at least 26 inches (66 cm) of FR-4 at 3.7Gbps (25% pre-emphasis) error-free exceeding the XAUI specification of 3.125Gbps over 20 inches (51 cm) of FR-4 backplane. "Our production parts show significant data rate margin to XAUI requirements, even across 40 inches (102 cm) of FR-4 backplane. Moreover, the additional bandwidth margin enables backplane designers to perform high-speed chip-to-chip bit-blasting in addition to permitting additional out-of-band signaling across the XAUI links," commented Kopec.

To document the superior characteristics of its SERDES technology, Lattice has also just released its new SERDES Handbook. This Handbook provides actual data on the typical eye diagrams, jitter, lock time, and other key operational aspects of the ORT82G5's SERDES block. It is available in electronic form on the Lattice website at www.latticesemi.com.

This seems to be the season for announcing embedded SERDES in PLDs, and related IP cores, and programs. Agere (now Lattice Semiconductor) and then QuickLogic with its QL82SD were the first to ship PLDs with embedded SERDES. These were followed by Cypress Semiconductor with its PSI (Programmable Serial Interface) devices, and then Xilinx with its Virtex-II Pro series.

Actel and Altera (see the following item) have both announced product families with embedded 3.125 Gbps SERDES. Actel has described its intentions in this area, but has not committed to a firm schedule. Altera, on the other hand, has stated that it will begin deliveries of the first parts from its seven-member Stratix GX family near the end of 4Q02 or early during 1Q03.

Xilinx recently has launched the Serial Tsunami initiative, which seems to be an umbrella for all of its related serial I/O activities. Applications covered by the initiative include serial backplane transceivers (Single and Quad 3.125 Gbps Transceivers), telecom transceivers (SONET OC-48 and OC-192), enterprise storage transceivers (Fibre Channel, Ethernet), and networking transceivers (Gigabit Ethernet, 10 Gb Ethernet, and InfiniBand).

The company has also recently released its Aurora reference design - a lightweight protocol designed to move data from point-to-point across serial links. In addition, the Serial Tsunami initiative will include IP core solutions for the major parallel and serial connectivity standards such as PCI Express, 1 and 10 Gigabit Ethernet (XAUI), and SONET and a serial connectivity training course, six development and characterization boards, complete 3.125 serial transceiver characterization data, and a dedicated serial design web portal.

Agere was very passive in its FPSC (Field Programmable System-on-a-Chip) devices marketing efforts. This situation has changed since Lattice acquired Agere's FPGA product lines. Cypress and QuickLogic have been relatively quiet since the initial announcement of their parts with embedded SERDES.

In April 2001, Cypress introduced its PSI family that integrated high-speed serial transceivers with its Delta39K CPLDs. The six PSI products were linked to CPLDs with a rated capacity of either 100K or 200K gates of programmable logic. Three high-speed parts in the family contained one or two 2.5 Gbps transceivers. The other three parts were described as frequency agile, and contained four or eight transceivers that could accommodate signals with data rates of 0.2 to 1.5 Gbps.

Lattice Semiconductor has just announced two new SERDES-based products and has issued some data attesting to the robustness of its ORT82G5. The ORT82G5, which is intended for 3.125 Gbps XAUI and Fibre-Channel applications, was initially released by Agere more than one year ago.

Lattice has added 850 Mbps SERDES capability to its line of ispGDX switches. This SERDES was developed at Lattice and is the same as the one used in its new line of FPGAs, the ispXPGA.

The 1.0 to 2.7 Gbps ORSO82G5 is a new part that was designed for SONET/SDH systems. The device combines the circuitry from an Agere ASSP with the same ORCA 4 FPGA section that is used in the ORT82G5. According to Lattice, the embedded SONET and payload processing elements consume about 1.5 million gates of ASIC logic - some 27% of the die area.

Lattice has one interesting feature in its 3.125 Gbps SERDES that is not included in either the Stratix GX or Virtex-II Pro devices. This is the ability to set the SERDES output voltage at one-half the normal value for chip-to-chip connections. The nominal output voltage for the Lattice and Altera parts is 1.5V, while the Xilinx devices have a 2.5V output from the SERDES.

The three different SERDES designs and output voltages result in very different power consumption characteristics. According to Altera, Stratix GX consumes 450 mW per four channels, while the Lattice parts consume 900 mW per four channels and the Xilinx SERDES consumes 1,400 mW per four channels.

Another very important difference among the three designs are the SERDES multiplex ratios. Both Lattice and Xilinx employ fixed multiplex ratios of 40 bits and 20 bits respectively. Altera claims that its multiplex data paths can be programmed to be 8, 10, 16, or 20 bits wide. The width of the data path is usually determined by the speed of the SERDES and the speed that the FPGA fabric can support. The slower the FPGA, the wider the path needed. Also, the amount of FGPA resources required for a given processing function depends on the width of the data path.