"With devices ranging from 4 to 20 high speed serial channels at speeds up to 3.125 Gbps and very low power consumption per channel, the Stratix GX family fits the bill in scaling up to a full high speed chassis or scaling down to the minimum requirement for a single line card," said Jeff Rhodes, business manager at Motorola Computer Group. "The flexibility of Altera's Mercury devices enabled us to implement our first generation Multi-Service Packet Transport Platform (MXP) in parallel with the emerging PICMG 2.20 switch fabric standard."

"The economics of 0.13-micron silicon are changing system architecture at a fundamental level, and the role of programmable technologies is becoming increasingly important as designers look for solutions that meet their requirements without painting them into a technological corner," said Jeremey Donovan, vice president and chief analyst with Gartner Dataquest's semiconductor group. "The melding of high-speed transceivers and programmable technology in particular is a logical outcome of the industry's new economic factors."

Low Risk Path to Multi-Gigabit Design
Designed with up to 20 full duplex transceiver channels the Stratix GX family is well equipped to handle high throughput datapaths. This includes high-speed backplane and chip-to-chip communication technologies that are rapidly emerging in high-speed, data-intensive applications. Combining Stratix GX devices with the powerful Quartus II design software and available intellectual property (IP) cores optimized for transceiver applications gives system architects the power to get high-speed systems up and running in minimal time. More than just a robust transceiver on an FPGA, Stratix GX is a complete design platform that includes Gigabit Ethernet XAUI or SONET IP cores, models for system verification, and board layout guidelines. These are critical elements that designers need to create a working transceiver based system for backplane or chip-to-chip applications.

Customer Defined Features
As with the Stratix and Cyclone FPGA families, Altera once again brought customers from a wide array of markets into the product definition process. Faced with a common challenge the need for reliable, high-speed data transfer across all design segments Altera designed Stratix GX devices to include features specifically identified by customers to be critical for successful design implementation.

Tuned for backplane applications
Stratix GX devices provide the rich features required for success in backplane applications; Stratix GX devices provide both 40-inch FR4 drive capability and receiver equalization. Devices also include hot-socketing capability.

Low transceiver power consumption
At 75mW per channel and only 450 mW per gigabit transceiver block, Stratix GX transceivers consume less than half the power of competing FPGA solutions. In addition Stratix GX devices support independent power down of either the transmit or receive channels. Low power consumption increases reliability and reduces cost.

Support for a high-speed protocols such as XAUI and SONET/SDH The Stratix GX architecture is the only FPGA and multi-gigabit solution in the industry that includes dedicated circuitry for backplane applications in both XAUI and SONET/SDH systems. XAUI-specific features include dedicated rate-matching, word-aligning, and clock-management circuitry. Devices include dedicated silicon to perform SONET/SDH pattern detection and SONET/SDH pattern transmission, and to support both an 8- and 16- bit wide data bus without the 8B/10B encoder/decoder. The dedicated circuitry increases reliability and provides time-to-market and cost advantages.

Hard DPA for source synchronous I/O pins
The industry's only embedded silicon implementation of dynamic phase alignment (DPA) circuitry provides a high-speed complement to the transceiver bandwidth. DPA simplifies high-speed board design and layout through the automatic elimination of skew introduced by unmatched trace lengths, jitter, and other skew-inducing effects. Hard DPA (vs. soft DPA) specifically provides better immunity to temperature or voltage variation and much lower power consumption.

The right logic densities for the transceiver channel count For high transceiver channel count applications, the Stratix GX architecture provides a more optimized channel to logic ratio than alternative solutions; Stratix GX devices provide reduced logic options due to the significant use of dedicated silicon to address both transceiver and source-synchronous applications.

"As the only second-generation product in the market, we're well ahead of our competitors. Stratix GX FPGAs have the advantage of including Altera's experience of having worked with customers implementing multi-gigabit transceivers into their designs," said Tim Colleran, vice president of product marketing at Altera. "Our intention is to pass on this experience as a competitive advantage to our customers building high-speed applications, allowing them to get their products to market faster, and with less risk."

Software Support
A beta version of Quartus II version 2.1 with support for Stratix GX has been shipping to customers since June of this year. A design kit specifically targeted for Stratix GX is now available through local Altera representatives as a complement to the Quartus II version 2.1 software. Quartus II version.2.1 provides support for system-level design with advanced features such as LogicLock, SOPC Builder, DSP Builder, board-level timing analysis tools, and signal integrity analysis tools. Quartus II provides the ideal development tool for meeting the design challenges of multi-million gate designs. It supports major operating systems such as Windows NT, Windows 98, Windows 2000, Sun Solaris, HP-UX and Linux operating system.

Packaging, Pricing and Availability
Stratix GX devices will be available in the 672-pin and 1,020-pin FineLine BGA packages. The first device, the EP1SGX25D in the 1,020-pin FineLine BGA package will begin shipping in Q1 2003. Devices in the family will be as low as $99 in 50K unit volumes by mid-2004.

Altera is promising to deliver Stratix-based parts with 3.125 Gbps SERDES that contains embedded circuitry for both XAUI and SONET/SDH implementations. The Stratix GX family contains eight members that are based on three different Stratix parts, the EP1S10, EP1S25, and EP1S40 that cover the capacity range from 10K to 40K logic elements. The smallest part is available with either one or two transceiver blocks, the middle device has either one, two, or four transceiver blocks, and the largest part contains either two or five transceiver blocks.

Each embedded transceiver block features four full-duplex channels capable of transmission speeds up to 3.125 Gbps using clock data recovery (CDR). Each channel has dedicated circuitry that implements various stages of the data recovery/transmission, serialization/deserialization, decoding/encoding, and synchronization processes. The receive channel contains a pattern detector/word aligner, rate matcher/channel aligner, 8B/10B decoder, and synchronizer blocks, each of which can be bypassed by the designer.

Altera has also added an embedded dynamic phase alignment (DPA) feature to the Stratix devices. This feature, which is used for source-synchronous connections, repeatedly compares incoming data with the system clock and continuously aligns the clock to match the data bits. DPA removes channel-to-channel and clock-to-channel timing variations introduced by unmatched board trace lengths, jitter, and other skew-inducing effects.

According to Altera, many interface standards organizations have incorporated DPA recommendations and requirements into their interfaces, including the Optical Internetworking Forum (OIF) with the System Packet Interface Level 4 (SPI-4) Phase 2 standard. Other interconnects requiring source-synchronous channels include HyperTransport, RapidIO, CSIX Streaming, and 10 Gbps Ethernet XSBI.

Altera expects that the Stratix GX parts with DPA will be able to operate at speeds up to 1 Gbps in the source-synchronous mode. Stratix GX devices have 22 source-synchronous channels with DPA for the EP1S10, 39 channels for the EP1S25, and 45 channels for the EP1S40.

Xilinx's Virtex-II Pro has a maximum source-synchronous data rate of 840 Mbps when used with its soft IP core for the SPI 4.2 standard. Altera claims that more than 3,000 logic elements are required to implement DPA in Virtex-II Pro.

Altera, Lattice, and Xilinx have adopted very different philosophies in implementing programmable devices around their embedded 3.125 Gbps SERDES. Lattice, by far, uses the greatest amount of embedded circuitry for its ORT85G5 and ORSO82G5 for XAUI and SONET/SDH applications, respectively. The XAUI implementation contains embedded state machines for both Ethernet and Fibre Channel systems. Altera's Stratix GX contains an embedded state machine for Ethernet, but must construct a state machine from the programmable logic for Fibre Channel implementations.

Lattice chose to develop separate parts for XAUI and SONET/SDH and married the embedded circuitry and SERDES to a relatively small programmable fabric of 10K ORCA 4 logic cells. Their parts will tend to be used for simple backplane implementations because of the small number of programmable gates available, especially since their SERDES multiplexes/demultiplexes into 40 data paths.

Xilinx, at the other extreme, has designed its Virtex-II Pro to use soft/firm IP cores to implement peripherals and buses for the embedded PowerPC and for the different communication system standards. This approach, according to the company, gives its customers the greatest flexibility and allows the FPGA platforms to be used while a standard is being developed. The Xilinx approach offers time-to-market benefits while the standards are in flux, but it tends to be expensive in terms of the use of programmable gates and the cost of the IP cores.