Luminance technology includes the patented modular array architecture, industry standard third-party tools, a rich portfolio of Lightspeed and third-party intellectual property (IP) and industry-renowned customer support.

"We designed our modular array ASIC approach to allow more design teams effective access to deep submicron technologies," said Dave Holt, President and CEO of Lightspeed. "Until Luminance, companies have been saddled with two expensive choices: slower, power-hungry FPGA prototyping solutions that are extremely expensive in volume production; or standard-cell ASICs with the inherent problems of development times up to 18 months and high NREs. We've solved these problems with a solution that delivers the fastest time to market at blazing fast speeds."

Utilizing a two metal mask, one via mask customization in conjunction with TSMC's .13u 8 layer copper, high performance CMOS process technology, Lightspeed's newest Modular Array ASIC will provide up to 10 million usable ASIC gates and up to five million bits of embedded dual-port RAM. The high-density architecture includes embedded PLLs, SRAMs and configurable I/O cells. These elements are optimized for maximum array efficiency that delivers an unparalleled degree of versatility for designing high-performance systems across a wide range of applications.

Luminance architecture excels in advanced I/O systems including the emerging standards such as SPI 4.2 and HyperTransport. Selected family members will have on-chip 622 Mb/s-3.2Gb/s SERDES. All family members are designed to support high performance flip chip packaging.

The underlying AutoTest structure ensures that 100% stuck-at-fault detection is accomplished without any design-for-test rules, user intervention or test overhead implications for the logic designer. Lightspeed's innovative AutoBIST technology enables the detection of path delay faults. Additionally, SiliconView allows in-system access to all chip states to assist with initial system bring-up and debug, allowing the designer to set states that are difficult to create through normal user-modes.

Lightspeed is continuing its efforts to bring the benefits of small feature size processes to the designer without the costs associated with a full cell-based ASIC design effort. The company is positioning its Modular Array families as FPGA alternatives, particularly targeting Xilinx devices. Like Virtex-II, I/Os in the new family can be set for a large number of different signaling standards, has built-in JTAG, and supports the digitally controlled impedance feature. Double data rate registers to support high-speed external RAM are included in the I/O cells.

Lightspeed, with some 70 people, is already in production supplying module-based ASICs. These are being made using 0.35-micron and 0.25-micron processes. While the company would not divulge its current revenues, it did state that nearly 200 customer designs have been completed. Approximately one-half of these have resulted from the conversion of FPGA (primarily from Xilinx) designs and the rest from ASIC designs.

With its latest release, the company is attempting to provide the benefits of a 0.13-micron process at NREs that are a fraction of those for the traditional ASIC approach. In the past, it has been doing this by using modules, rather than gates, as the basic building blocks and interconnecting these with only two layers of metal. The new 0.13-micron Luminance family will require three metal layers to configure the logic within the modules and to provide the required connectivity. AMI, with its XP line, and NEC, with its ISSP family, also offer module-based ASICs that can be customized with a few metal layers.

The module approach permits the company to stock wafers that only need the final three metal layers, significantly shortening the time required to deliver the first devices. NRE charges will be about $250K, one-third to one-quarter of those for a traditional 0.13-micron cell-based ASIC.

In addition to the lower NRE charges, short turn around times for first silicon, and a simplified design flow, Lightspeed does not require the user to provide test vectors. The company uses proprietary built-in test circuitry and boundary scan logic that enables it to generate the required test vectors with 100% stuck-at-fault test coverage.

The Luminance family is being produced on TSMC's 0.13-micron, 8-layer copper process using its1.0V HS (high-speed) logic process. Luminance parts run at a core voltage of 1.2V and have the capability to set I/O signal voltages at levels up to 3.3V. The company claims that the performance of designs in the new devices will be comparable to 0.15-micron designs. The 700 MHz claim is based on 10 levels of logic. Lightspeed expects that most the Luminance designs will be for performance levels that are less than one-half of the 700 MHz claim.

Lightspeed has received a 0.13-micron test chip that was produce using TSMC's CyberShuttle program. The company is now accepting customer designs and expects to be able to start production deliveries during 1Q03. It will be banking eight-inch wafers for rapid customer delivery.

The company has not yet completely defined the Luminance family, but it will probably contain 6 or 7 parts with different amounts of user configurable logic and embedded memory. It is expected that the family will extend to 10 million usable ASIC gates with 5 Mbits of dual-port embedded memory. Lightspeed expects the family to be most attractive to those customers needing several 100K production parts.

Luminance has been designed to function as a replacement for Xilinx's Virtex-II family as well as a low NRE cost ASIC. The I/Os can be configured to support a wide variety of signaling standards. LVDS and LVPECL speeds of 1.244 Gbps can be achieved. These speeds are significantly higher than those that can be obtained with Virtex-II. Also, Luminance will contain 16 separate I/O banks versus 8 for Virtex. Like Virtex, the I/O's impedance can be digitally controlled.