AES, DES and Triple DES IP Complement Actel's Existing FPGA Design Security

SUNNYVALE, Calif., Nov. 25 -- Furthering its commitment to offer secure solutions to the marketplace, Actel Corporation announced the availability of new Advanced Encryption Standard (AES) and Data Encryption Standard (DES) intellectual property (IP) cores optimized for Actel's nonvolatile Axcelerator, ProASIC, ProASIC Plus, RTSX-S and SX-A field-programmable gate array (FPGA) architectures.

Through Actel and its partners, Amphion Semiconductor, Inc. and Helion Technology, customers now have access to design services and a range of encryption cores certified by the National Institute of Standards and Technology (NIST) that support AES, DES and triple DES (3DES) algorithms. With a wide variety of configurations, these flexible IP cores offer users high-performance data encryption for wireless and wire-line communications, including e-Commerce, secure enterprise networks and personal security devices.

"To safeguard against reverse engineering, cloning and overbuilding, Actel's nonvolatile antifuse- and flash-based FPGA architectures offer exceptional levels of design security protection. Often, our customers are also interested in securing and authenticating their data streams," stated Dr. Yankin Tanurhan, senior director, IP solutions at Actel. "The introduction of these new AES, DES and triple DES encryption cores further underscores Actel's commitment to deliver secure solutions for a wide range of applications in the communications, consumer, military, aerospace, aircraft and industrial markets."

"It's quite conceivable that every mobile communicator, server and Internet-enabled appliance in the worldwide communications infrastructure will embed high-performance encryption technology in some form or other," said Dr. J. G. Doherty, president and chief executive officer at Amphion. "Coupled with the inherent design security of Actel's FPGAs, these AES, DES and triple DES solutions are ideal for applications that require maximum levels of data privacy."

"We see a growing demand in the industry for high-performance encryption functions to secure data for e-Commerce transactions, secure enterprise networks and personal security devices," said Graeme Durant, chief executive officer at Helion. "Our customers, such as Ember Corporation, have already benefited from the security advantages offered as a result of the implementation of our standard AES encryption core optimized for Actel's nonvolatile devices."

"After evaluating Actel's flash-based FPGA architecture, it is clear that ProASIC offers the low power, security and nonvolatility that competitive solutions are unable to deliver," said Jeffrey Grammer, president and chief executive officer at Ember Corporation. "With Actel's ProASIC FPGA and Helion's standard AES IP core, we are now able to offer our customers high-performance, secure solutions for their embedded wireless sensing and control applications."

Encryption Solutions

Actel has developed the new CoreDES and Core3DES IP cores for its Axcelerator, ProASIC Plus, SX-A and RTSX-S FPGA devices. Each core includes encryption and decryption capabilities and supports 56-bit and 168-bit keys, respectively.

Amphion Semiconductor, a leading provider of semiconductor IP for digital video and broadband wireless, has optimized its high-performance AES, DES and 3DES solutions for Actel's Axcelerator, ProASIC Plus and SX-A FPGA families. The AES encryption and decryption cores are available in standard, compact, high-speed and ultra high-speed versions, enabling customers to choose an implementation that best fits their specific application. Designed to operate in either DES or 3DES mode, four DES/3DES solutions are available -- ultra compact, compact, high speed and ultra high speed.

Helion Technology, a consulting firm with expertise in the development of IP cores for data security applications, is offering three certified AES encryption solutions -- Tiny AES, Standard AES and Fast AES. These cores are available as highly optimized netlists for use with Actel's Axcelerator, ProASIC, ProASIC Plus and SX-A families.

Core Availability

Actel has now turned its attention from trying to sell SRAM-based FPGA cores for use in ASICs and/or ASSPs to replenishing its stock of IP cores for its antifuse and ProASIC FPGAs. In addition to announcing its encryption cores, the company has announced the availability of 50 new cores for communication, embedded, and consumer applications.

These cores were developed by Actel and seven independent IP core providers that include Amphion Semiconductor, CAST, GDA Technologies, Helion Technology, Inicore, Memec Design, and MoreThan IP. The 50 new cores include;

--Forward error correction (FEC) technology, such as Reed Solomon encoders and decoders, 10/100/1G Ethernet MAC controllers, Packet-Over-SONET Layer 2, HDLC controllers and PL3 and Utopia Level 3 interfaces for use in communications applications, including wireless LANs, xDSL, SONET/SDH and DWDM.

-- PCI, 8-bit microcontrollers, UARTs, DMA, and CAN and USB controllers for use in embedded systems applications.

-- MPEG 2, digital video broadcast (DVB) modulators, memory controllers and encryption cores for use in consumer applications, including multimedia systems and personal security devices.

Actel is now offering some 22 cores for DES, 3DES, and AES security applications. The DES and triple-DES cores were the defacto encryption standards until early in 2001. At that time, the Rijndael algorithm was selected by the National Institute of Standards and Technology as the Advanced Encryption Standard (AES) to replace DES.

Rijndael, a block cipher, was chosen after a study of five algorithms. It proved to be both the fastest algorithm and offer the most efficient hardware utilization. The claim is that Rijndael can be used in all applications where a high degree of security is desired - stronger, in fact, than triple-DES - but where hardware resources are limited. AES uses a higher number of bits for encrypting each key than other methods and also offers performance advantages across a broad range of applications.

Last year, Amphion introduced four different versions of the encryption and decryption Rijndael cores. These are a standard general-purpose core that can be implemented with 128-bit, 192-bit or 256-bit keys; a compact version for a 128-bit key; a low latency version; and an ultra fast version.

When implemented in an ASIC, the Amphion compact core requires 14.8K gates, runs at 200 MHz, and requires 44 cycles for each operation. The resultant data rate is 581 Mbps. The heavily pipelined ultra fast core, by comparison, uses 203K gates and can complete each operation in one cycle. It's data rate is 25,600 Mbps.