Xilinx Delivers New Adaptive I/O Solution to Reduce Serial Design Cost and Improve Time to Market

Innovative Solution Demonstrates Benefits of Combining the PowerPC Processor and 3.125Gbps Serial Transceivers Only Available In the Virtex-II Pro Platform FPGA

SAN JOSE, Calif., Jan. 15 -- Xilinx, Inc. today announced the availability of a new adaptive I/O solution, enabling system designers to automate the process of fine tuning serial I/O to achieve maximum system performance. The solution includes three new reference designs, addressing applications such as communication line cards where the highest level of interoperability among various suppliers' chips is critical to the overall cost, development time and performance of systems. Part of the Xilinx Serial Tsunami initiative, the solution helps designers easily migrate to serial technology and will be discussed at the upcoming Platform Conference held at the Silicon Valley Conference Center in San Jose, CA on January 28th and 29th, 2003

"Leveraging the embedded PowerPC processor and 3.125Gbps serial transceiver embedded into the Virtex-II Pro Platform FPGA, this innovative solution now allows designers to optimize system performance and reduce design cycles in both the diagnostic and deployment phases of system design," said Andy DeBaets, senior director of applications and systems engineering at Xilinx. "Not only does this solution reduce the overall cost of system design, but it also improves customers' time to market."

The reference designs underscore Xilinx's commitment to support the broad industry trend toward serial connectivity -- dubbed it's Serial Tsunami initiative -- which is being driven by companies across a wide range of industries as a means to reduce system costs, simplify system design, and provide scalability to meet new bandwidth requirements.

Adaptive I/O in diagnostic phase

This reference design uses the embedded PowerPC processor to test and analyze the serial link integrity using a bit error rate tester (BERT) and then dynamically modify attributes of the serial transceivers to achieve maximum system performance. Customers can also use an available hyper terminal interface to modify the settings. The modifiable settings include values for programmable pre-emphasis and differential swing control. For more information on these parameters, visit the RocketIO user guide at "http://i.cmpnet.com/chipcenter/pld/products_700-799/www.xilinx.com/publications/products/v2pro/userguide/ug024.pdf".

Bit error rate tester

This reference design provides a two-channel Bit Error Rate Tester (BERT) module for generating and verifying high-speed serial data transmitted and received by the serial transceivers. Frame counters in the receiver track the total number of data words, or frames, received and the total number of data words having bit errors and being dropped. The embedded PowerPC processor reads the status from the BERT and can interact with the user using a PC's hyper terminal.

Adaptive I/O in mission mode

With this reference design, the serial transceivers on the Virtex-II Pro FPGA can be dynamically reconfigured using the data acquired during the diagnostic phase. It offers customers a way to fine tune system performance during the deployment phase, e.g. a Virtex-II Pro based communications line card plugged into a backplane slot can have the serial I/O parameters changed for the best performance depending upon the location of the slot it is plugged into.

The moves from parallel interconnect systems to serial ones are well underway. Reductions in both package pin counts and board area and higher throughputs are the primary advantages of the serial approach. However, implementing systems with MGTs (multi-gigabit transceivers) running at 3.125 Gbps is not like taking a walk in the park - it is more like trying to make your way through a swamp full of alligators.

The transmission lines from and to the MGTs must be properly terminated to prevent reflections that can result in transmission errors and/or coupling to adjacent lines and other signal integrity related problems. Different positions in a card cage or slight changes in the device being driven can have a marked impact on transmission errors.