Small form factor, single chip solution saves board space

Highest design security against reverse engineering and IP piracy

SUNNYVALE, Calif. - February 03, 2003 -- QuickLogic Corporation, the pioneer of ESPs (embedded standard products), today announced the availability of the Eclipse-II FPGA family to address applications that demand ultra-low power, small form factor packaging, and high design security. Eclipse-II FPGAs exceed the functionality previously addressed by Complex Programmable Logic Devices (CPLDs) and FPGA devices while providing significant power and cost savings. With an architecture that features dedicated SRAM blocks, flexible clock architecture and ultra-low power consumption, the Eclipse-II family offers FPGA, CPLD, and ASIC designers multiple solutions for their applications.

"Our patented ViaLink interconnect technology enables QuickLogic to deliver the lowest power, most routable FPGA in the industry," said Brian Faith, Quicklogic's Manager of FPGA products. "The low power architecture of Eclipse-II provides developers of mobile, portable, wireless, and hand-held systems with a feature-rich alternative to CPLDs and ASICs. In addition, the low power consumption (i.e. 250 (A standby current) of Eclipse-II FPGAs enables designers to reduce system costs by using smaller, less costly voltage regulators and power sources."

The Eclipse-II family is available in small form factor packaging, giving system developers the benefits of a low power, high-performance FPGA without sacrificing board space. This packaging makes the devices ideal for miniaturized portable consumer products. Unlike some other FPGAs, the Eclipse-II devices do not require an external memory to retain the FPGA configuration data, thereby saving additional board space and power consumption. A single-chip solution means less board area, which in turn reduces end-system cost for designers.

Armed with QuickLogic's patented non-volatile ViaLink interconnect technology, Eclipse-II FPGAs provide exceptionally high levels of design security from reverse engineering and IP theft. Additional architectural features in the Eclipse-II FPGA family afford users the highest level of design security, above and beyond that of ASICs.

Flexible, High Performance Clock Architecture

One of the most difficult challenges in system design today is how the multitude of clock domains are distributed and managed. Towards this end, Eclipse-II devices are equipped with a large number of distributed clocks enabling designers to bridge up to 20 clock domains in a single Eclipse-II FPGA. In addition, the flexible clocks networks can drive user-programmable Phased Locked Loops (PLLs). These PLLs can be programmed for clock frequency multiplication, division and be used to improve your design's I/O performance. Eclipse-II PLLs not only reduce chip-to-chip delays in high performance systems, they also reduce the number of components on a designer's board, thus further reducing end-system costs.

Eclipse-II ApplicationsThe Eclipse-II FPGA family addresses a wide range applications such as mobile, wireless, handheld, portable, medical equipment and defined form factors such as PCMCIA, CardBus, MiniPCI, and SDIO.

Software and Intellectual Property Support

QuickLogic provides designers with QuickWorks an intuitive, easy-to-use development environment including schematic entry, simulation, synthesis, accurate power calculation, timing driven placement and routing, and static timing analysis tools. The Eclipse-II FPGA family is supported in QuickWorks version 9.4, and is available now for download from "http://i.cmpnet.com/chipcenter/pld/products_700-799/www.quicklogic.com". QuickLogic offers several IP blocks for use in QuickLogic FPGAs such as PCI, memory interface, DSP and other commonly used functions.

Pricing and Availability

Eclipse-II is basically a shrink to a 0.18-micron process of QuickLogic's earlier 0.25-micron Eclipse series of antifuse FPGAs. There are, however, two major differences between the families. One is that the company has made it possible to deactivate the internal charge pump to reduce the standby current.

The second relates to the makeup of the new series. Eclipse-II is structured to serve simpler, lower capacity applications than Eclipse. The original Eclipse family contained four members with capacities ranging from 906 to 4032 logic cells. Eclipse-II has five members with capacities ranging from a low of 128 to a high of 1,536 logic cells. The two largest members of the new series, the QL8250 and QL8325, correspond to and are compatible with the two smallest members of the Eclipse family.

The basic logic cells use in QuickLogic's antifuse FPGAs is much more complex than the look-up-table/register cells used in the SRAM-based parts from Altera and Xilinx. The logic cells contains two six-input AND gates, four two-input AND gates, seven two-to-one multiplexers, and two D-type registers. The multiplexers can be used to segment the cell for the mapping of multiple small logic functions onto a single cell. The cell has a fan-in of 30 and can handle functions with 17 simultaneous inputs. The cell has six outputs, two of which are registered.

The actual logic capacity of each cell lies between 30 and 40 gates, depending on the design being implemented. This puts the gate capacities of the Eclipse-II family in the 4K- to 62K-gate range. The low end of the range has a capacity that is comparable to a moderate density CPLD.

Pricing for Eclipse-II will be comparable to equivalent density CPLDs. The projected large quantity production prices for the parts are $3.50 for the QL8025, $ 5.25 for the QL8050, $ 8.75 for the QL8150, $ 13.00 for the QL250, and $17.50 for the QL8325.

QuickLogic has been able to substantially reduce the static current drawn by the Eclipse-II devices by including a provision that turns off the charge pump for the on-chip high-voltage supply. The standby current is reduced to 250-500 uA when this feature is activated. According to the company, this compares with a standby current of 30-300 mA for Xilinx's Spartan II/IIE FPGAs.

Another important consideration in portable applications is the current drawn during power-up. The claim is that Eclipse-II parts draw less than 20 mA during power-up, compared to more than 500 mA for the Spartan devices. QuickLogic admits that Xilinx's CoolRunner-II family of CPLDs, with a standby current of less than 100 uA, is a lower power solution, but claims that those parts do not have the capacity required for many portable applications.