- Power consumption only 20% of current low power CPLDs, ideal for battery-based products

- Family provides programmable solutions for portable and handheld electronics -

Hillsboro, Or- January 20, 2003 - Lattice Semiconductor Corporation, the inventor of in-system programmable (ISP) logic products, today announced the immediate availability of the first member of its 1.8-volt ispMACH 4000Z CPLD family that sets a new standard for the industry's lowest static power consumption. The ispMACH 4032Z device is the first of three initial ispMACH 4000Z devices, which span logic capacities from 32 to 128 macrocells.

These breakthrough devices provide extremely low static current consumption (20 microamps worst case for a 32 macrocell device) and cost effective logic implementation demanded by handheld and portable applications. By reducing static power consumption to only 20% of previous devices, the new family dramatically expands the application scope of programmable logic in the portable and handheld arenas and provides new programmable solutions within the $6.9 Billion portable consumer semiconductor market as well as other power-conscious segments. These ultra-low power features are also coupled with high-speed operation: the ispMACH 4032Z device provides 3.5ns pin-to-pin delay (tPD), 3.0ns clock-to-output delay (tCO), 2.2ns set-up time (tS), and 265MHz operating frequencies (fMAX).

Traditionally, requirements for low standby power and low cost have limited the use of PLDs in handheld and portable equipment. "The ispMACH 4000Z combines the industry's lowest static power with an extremely cost effective solution," said Stan Kopec, Lattice vice president of corporate marketing. "It is suitable for a wide variety of handheld, portable, and consumer products. At only one-fifth the power consumption of current low-power CPLDs, it will dramatically expand the applications that programmable logic can address within these markets."

The ispMACH 4000Z is targeted for applications including cell phones and peripherals, paging devices, GPS positioning equipment, PDAs, digital still camera's, digital video camera's, personal audio equipment, portable medical equipment, automotive telematics and radio, and industrial instrumentation.

Industry's Lowest Static Power Consumption / Fastest Performance

Standby time is a key design requirement for portable and handheld equipment. Designers want to minimize the standby or static power associated with logic within their designs to maximize the interval between battery charges or replacement. In designing the ispMACH 4000Z, Lattice took its popular ispMACH 4000 architecture, re-optimized its non-volatile E2CMOS process technology and redesigned key circuit elements to reduce static power by over a factor of 50. As a result, the maximum static current consumption for devices in the family ranges from 20 to 30 uA over the commercial operating temperature range, while still maintaining the industry's fastest performance for a low-power CPLD solution.

Power Supply and I/O Standard Support

The ispMACH 4000Z operates from a nominal 1.8-volt power supply with operation extended down to 1.5-volts, accommodating the end of battery life voltage of certain systems. The ispMACH 4000Z devices have two I/O banks, each with their own power supply voltage that can be set at the appropriate voltage to support LVTTL and LVCMOS 3.3, 2.5, and 1.8-volt outputs.

The device input buffers have programmable thresholds that support the above standards independent of the I/O bank voltage. Extended range 3.3-volt I/O are supported instead of the more common narrow range version of the standard, again accommodating the end of battery life voltages associated with certain systems. The I/Os on the ispMACH 4000Z are 5-volt tolerant to also facilitate connection to legacy chips and interfaces

All ispMACH 4000Z devices are Boundary Scan Testable and in-system programmable through an IEEE 1532-compliant JTAG boundary scan (IEEE 1149.1) interface.

Design Tools

The ispMACH 4000 product line is supported by Lattice's new ispLEVER design tools. The ispLEVER tools, Lattice's platform for next-generation logic design, provide designers with rapid access to the performance of the ispMACH 4000Z devices while maximizing resource utilization. This is achieved through timing driven placement & routing coupled with optimized synthesis support from vendors such as Exemplar and Synplicity. Additional third-party EDA tool support is provided through industry standard EDIF netlist import and export. The ispLEVER software is available in PC as well as UNIX workstation versions.

Price and Availability

Even though Lattice identifies a $6.9 Billion market for semiconductors used in portable equipment, it should be understood that much of this market is not really available to the producers of PLDs. The market for semiconductors used in portable equipment is dominated by their use in cellular telephone handsets. The majority of these handsets are produced for the low end of the market, where the logic is implemented in cell-based ASICs.

There are, however, a plethora of consumer and other portable electronic equipments where PLDs can and do play a significant role. Features are continually being added to such portable consumer products as cell phones, PDAs, camcorders, digital cameras, and MP3 players, which can combine various audio, digital and video functions.

Shrinking product life cycles have become standard for these products. Some products are unsuccessful, while others are supplanted by products with new features. The result is that often the quantities being produced are modest and there is little time to accommodate an ASIC development program. Another factor that makes this a fertile ground for PLDs is the changing interface standards that mark the wireless home networking environment.

Xilinx was one of the first PLD companies to pursue low-power applications with its 1.8V CoolRunner-II series of CPLDs. This series uses an all-CMOS structure to achieve its low static current. The technology is derived from the XPLA3 CPLDs, which Xilinx acquired from Philips Semiconductor.

The CoolRunner-II family spans the 32-macrocell to 512-macrocell range. Lattice's announced plans for its 1.8V ispMACH 4000Z CPLDs state that the family will range in size from 32 to 128 macrocells. CoolRunner-II, with a Fmax of 333 MHz for the 32-marcocell part, is somewhat faster than the corresponding size ispMACH 4000Z.

Lattice's new family really shines when comparing the specifications for the static current drawn for ispMACH 4000Z and CoolRunner-II. Lattice guarantees that a static current of less than 20 uA under all conditions for the 32-macrocell part. The static current specification will increase to 30 uA for the 128-macrocell ispMACH 4000Z.