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Lattice Launches Mixed-Signal PLD

The manufacturer says . . .
Murray Disman says . . .
LATTICE SEMICONDUCTOR LAUNCHES FIRST MIXED-SIGNAL PLDs OPENING POWER MANAGEMENT MARKET

- Device integrates key programmable analog and logic functions to provide innovative power supply monitoring and sequencing control -

HILLSBORO, OR - JANUARY 20, 2003 - Lattice Semiconductor Corporation, the world's largest supplier of in-system programmable devices, today announced the launch of a revolutionary new family of ispPAC devices for power management. These devices are the industry's first mixed-signal programmable logic devices (PLDs). Featuring in-system programmable analog and logic blocks, the new devices provide optimized power supply management functions critical to the operation of today's multiple power supply electronic systems and provide unique programmable control solutions within the $12 Billion power semiconductor market. Through a combination of programmable logic, voltage comparators, references, and high voltage FET drivers, the devices support single-chip programmable power supply sequencing and monitoring.

Many advanced integrated circuits such as microprocessors, DSPs, FPGAs and ASICs employ multiple power supply voltages to maximize performance while minimizing power consumption. These voltages must be applied to the devices and removed in pre-defined sequences to avoid damaging the devices. The first device in this new ispPAC family, the ispPAC-POWR1208, integrates Lattice Semiconductor's industry-leading ispMACH CPLD and ispPAC programmable analog technologies, resulting in a single chip that implements a flexible, cost effective, and convenient solution for this problem. With a "supply-ruggedized" ispMACH PLD at its core, the ispPAC-POWR1208 device features 12 precision analog threshold comparators with on-chip voltage references for supply monitoring, 4 noise-immune digital inputs and 4 open-drain digital outputs for system control interfacing, 4 programmable (both maximum voltage and ramp rate) high voltage FET drivers for supply control and 4 programmable timers with an on-chip 250 kHz oscillator for delay control. The device has been ruggedized to operate in noisy power supply environments from 2.25V to 5.5V and is packaged in a 44-pin Thin Quad Flat Pack (TQFP) package.

"Controlling multiple supply voltages as required by most advanced integrated circuits today is complicated and a burden for today's designers," said Stan Kopec, vice president of corporate marketing for Lattice Semiconductor. "The ispPAC-POWR1208 single-chip programmable solution provides unprecedented convenience for power supply management on any circuit board and expands the programmable market into a major, untapped segment. Our PAC-Designer PC-based software makes using this incredible capability a snap."

ispPAC-POWR1208 Applications

The ispPAC-POWR1208 features make it ideal for controlling multiple power supplies. As such, its applications span all types of electronic equipment, including telecom and networking systems, storage systems, servers, test equipment and automotive electronics. Used in conjunction with N-channel switching FETs and/or LDO (Low Drop Out) regulators, the ispPAC-POWR1208 provides a compact power supply control solution. It easily replaces current solutions using multiple analog and digital integrated circuits as well as numerous resistors and capacitors, reducing cost while increasing reliability and flexibility.

ispPAC-POWR1208 is Supported by PAC-Designer Version 2.0 Software

Power supply sequencing and monitoring designs can be implemented on the ispPAC-POWR1208 device using Lattice's popular PAC-Designer version 2.0 software. The PAC-Designer software is an intuitive schematic design entry and simulation tool. The user can design complex sequencing and monitoring functionality easily using PAC-Designer's newest feature, LogiBuilder, which provides a series of easy-to-use pull-down menus. Designs can be completely verified using the tool's built-in waveform simulator. The free PAC-Designer software is available for download from www.latticesemi.com.

PAC-System Development Kits

The PACsystemPOWR1208 is a low cost development tool designed to enable designers to build quick prototypes of their circuit implementation and to check its functionality. The design implemented using PAC-Designer is downloaded into the device through the ispDOWNLOAD cable that connects to the PC's parallel port.

The PACsystemPOWR1208 contains an evaluation board for the ispPAC-POWR1208, an ispDOWNLOAD cable, and PAC-Designer v2.0 software.

Price and Availability

Prices for the ispPAC-POWR1208 device starts at <$10.00 in 10,000 piece quantities. Samples of the ispPAC-POWR1208 in a 44-pin TQFP package (Industrial temperature grade, -40(C) to +85(C) are available immediately. The ordering part number is ispPAC-POWR1208-01T44I.

PACsystemPOWR1208 evaluation kits are also available through authorized Lattice distributors or on the Lattice web site at a suggested retail price of $149.

Lattice has released a unique device that combines programmable analog circuitry with a portion of an ispMACH CPLD. The PLD section in the ispPAC-POWR1208, which can be used to control the states of the sequencer state machine or for other control and monitoring functions, is relatively small with 16 macrocells. The AND array in the CPLD can accept up to 36 inputs and produce up to 81 product terms that feed the macrocells.

The company also plans on adding a smaller version of the ispPAC-POWR1208 in the future. This part, the ispPAC-POWR604, has 6 instead of 12 power supply sense inputs and 2 reprogrammble timers instead of 4. The CPLD section is only half as large with 8 macrocells. The smaller device does not contain the high-voltage FET drivers.

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