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Altera Delivers Nios Version 3.0

The manufacturer says . . . Murray Disman says . . .

Altera Delivers the Goods with Nios Processor Version 3.0, Industry's Leading Soft-Core Processor
New Features Based on Extensive Feedback from the Growing Nios Processor Development Community
SAN JOSE, Calif.--Feb. 18, 2003--Extending its embedded-processor leadership even further, Altera Corporation announced the release of version 3.0 of the Nios embedded processor, the industry's leading soft-core processor. The newest version of the Nios embedded processor includes features that take advantage of the advanced memory features on the high-performance Stratix and low-cost Cyclone device families for improved system performance, while delivering new tools for faster system development.
More than 10,000 Nios embedded-processor hardware development kits have shipped to customers to date, confirming that the community of designers standardizing on Altera's soft-core processor for their embedded applications is growing at an unprecedented rate. It is this audience that has provided significant feedback to the feature set, user interface, and performance enhancements delivered in version 3.0 of the Nios embedded processor.
"We had previously used off-the-shelf processors in our designs, but we have since switched to the Nios processor for greater integration, more flexibility, and its ease of use," said Douglas Horne, vice president of research and development at BioMeridian. "Currently, we are using the Nios processor in our MSAS-Professional and MSAS-Partner products. These products are battery-powered, which means reducing power consumption was a priority. The ability to add custom instructions to the Nios processor helped us achieve high data throughput while keeping the clock speed low enough to reduce power use by 66 percent."
Nios Embedded Processor Version 3.0 Features

User-Configurable Caches—Version 3.0 of the Nios embedded processor includes user-configurable, level one (L1) instruction and data caches that take advantage of the large dual-port memories on both the low-cost Cyclone and Stratix devices for higher performance system requirements.
Enhanced SDRAM Controller—Nios embedded-processor developers can achieve single-cycle access to low-cost SDRAM devices at speeds above 100 MHz. The combination of the user-configurable L1 caches and SDRAM controller allows designers to use inexpensive, off-chip memory, and achieve nearly the same performance for large memory requirements as running from high-performance, on-chip SRAM.
Enhanced Avalon Switch Fabric—The Avalon switch fabric, Altera's parameterized interface bus used by the Nios embedded processor, can now support pipelined data transactions to eliminate data bottlenecks. The support for posted-read and posted-write operations enables fast access to low-cost, external SDRAM devices, significantly improving the performance of complex processor subsystems.
New JTAG-Based Real-Time Debugger—The JTAG-based OCI (On-Chip Instrumentation) core from First Silicon Solutions (FS2) included in the new version of the Nios embedded processor gives software developers a powerful tool for debugging real-time code. The OCI is accessed through a JTAG target connection, and supports in-circuit-emulator features such as complex hardware triggers and real-time trace.
Robust Integrated Development Environment—Support for Accelerated Technology's code|lab Developer Suite allows software engineers to quickly edit, compile, download, and debug their Nios processor-based code, providing native support for the advanced real-time debug and processor trace capabilities of the OCI debug core.
Network Protocol Software Library Included—Software support for many Ethernet protocols, including APR, IP, ICMP, TCP, UDP, and raw Ethernet, formerly a $495 accessory kit, is now included with Nios processor version 3.0.

"With this new release, software developers will be able to immediately benefit from the complete code|lab Developer Suite and Nucleus real-time operating system," said Robert Day, director of marketing for the Embedded Development Division of Mentor Graphics.
"The OCI that we developed for the Nios core provides a rich set of debug features normally associated with very expensive in-circuit emulators," said Rick Leatherman, president of FS2. "Equally important, the OCI is scalable, allowing designers to optimize the feature mix and gate count requirements for their particular design."
Craig Lytle, vice president of Altera's intellectual property (IP) business unit, commented on the growing Nios community, "Since its introduction in Fall, 2000, the Nios processor has become a huge success, with many of our key customers having completed multiple Nios designs. More and more customers are jumping on the Nios processor bandwagon because they like the performance, flexibility, and cost. As a result of our ongoing dialog with these customers, the Nios processor version 3.0 includes the features that they need and want the most."
Pricing and Availability
Active Nios embedded processor subscribers will receive version 3.0 immediately, and expired subscriptions can be renewed for only $495 to receive an additional one year of updates. Version 3.0 of the Nios embedded processor will be shipping in March, with the new Nios Development Kit, Stratix Edition, available for $995 from Altera and its distributors. The code|lab Development Suite, ISA-NIOS debug probe, ISA-NIOS/T trace probe, and Nucleus PLUS real-time operating system (RTOS), are available from Accelerated Technology at www.acceleratedtechnology.com.

Nios has been a super success for Altera. The company says that it has exceeded its expectations by a factor of five by shipping 10,000 Nios development kits in about 2½ years. It also claims that a number of customers have double-digit designs in development or in production. Many of the customers are new to Altera and, in some cases, are new users of FPGAs.
Nios is a relatively simple and inexpensive configurable RISC processor that can run at speeds greater than 125 MHz, and features a 16-bit instruction set and user-selectable 16- or 32-bit data paths. The 16-bit data-path version consumes less than 1000 logic elements (about 10K logic gates), and the 32-bit version uses less than 1500 logic elements (about 18K logic gates). Altera claims that a typical 32-bit data-path Nios processor will consume only $2.00 worth of logic in one of the company's Cyclone devices. The Nios embedded processor is royalty-free when used in one of Altera FPGAs or in its HardCopy ASIC alternatives.
Two of the key elements in the Nios design kits, which sell for $995, are the SOPC Builder design tool and the Avalon interconnection scheme. SOPC Builder allows the designer to choose from a library of configurable peripheral elements that are then interconnected automatically with the CPU and memory using the Avalon switch fabric. SOPC Builder can now access some 33 cores, which Altera plans to expand to 100 cores.
The Avalon switch fabric logic can include capabilities for data-path multiplexing, address decoding, wait-state generation, dynamic-bus sizing, interrupt-priority assigning, and advanced switch-fabric transfers. Avalon permits multiple simultaneous operations, and can establish dedicated or shared data paths.
Altera is relying on data-path optimizations, custom instructions, and hardware acceleration, rather than raising the operating frequency of the processor, to increase Nios performance. It estimates that optimizing the data path through the use of the Avalon switch fabric can increase performance by a factor of ten; the use of custom instructions for such operations as bit manipulations and CRC check sum can yield a 60 times increase, and hardware acceleration for FIRs and MACs can boost performance by up to 500 times.
The instruction and data caches are user-configurable in sizes ranging from 1K to 16K. Version 3.0 will use the dual-port memories present in the Stratix and Cyclone families of FPGAs. A Nios development board containing an EP1S10 Stratix device has recently been released. One containing a Cyclone FPGA will be released in the near future.
The first in a series of Nios development kits targeted for specific device families, the Nios Development Kit (Stratix Edition) includes a Stratix development board that features the Stratix EP1S10 device, 1 Mb of SRAM, 16 Mb of SDRAM, 8 Mb of flash, a 10/100 Ethernet port, two serial ports, a Mictor connector for software debug, two expansion headers, power supply, and download cable.
The Stratix Edition kit supports a set of software development tools from Accelerated Technology, including the Nucleus RTOS and the code|lab Developer Suite. The code|lab software features native support for First Silicon Solutions' (FS2) BlackBox debug probe and support for Altera's ByteBlaster MV download cable for software debug. Also included is an evaluation version of the IAR visualSTATE development software, featuring a graphical state machine diagramming tool that generates a C model of the user's state machine to accelerate software generation.

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