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Xilinx Hits 10 Gbits/s

The manufacturer says . . . Murray Disman says . . .

Xilinx Announces Breakthrough 10 Gbits/s Technology
World's first programmable logic supplier to demonstrate 10 Gbits/s working silicon
SAN JOSE, Calif.--Feb. 24, 2003--Xilinx, Inc., the world's leading provider of programmable IC and programmable system solutions, announced the successful demonstration of serial technology at 10 Gbits/s on a single channel. Xilinx is the first PLD vendor to demonstrate 10 Gbits/s technology using a standard CMOS logic process. This announcement represents a major milestone in the Xilinx Serial Tsunami initiative, and further extends the company's leadership position in high-speed serial solutions. Based on Non-Return to Zero (NRZ) signaling, this technology supports industry-leading chip-to-chip, chip-to-module, and serial backplane applications. Xilinx plans to deploy its groundbreaking 10 Gbits/s circuitry in products slated for delivery this year.
"Serial solutions will ultimately be deployed in nearly every electronic product imaginable," said Wim Roelandts, president and CEO at Xilinx. "The inherent scalability and cost advantages of high speed serial make this technology imperative for current and next-generation telecommunications, networking, and storage applications."
Analysts agree that the serial I/O wave is inevitable. Parallel I/O schemes reach physical limitations at speeds greater than 1 Gbits/s, no longer providing a reliable and cost-effective means for high-speed signaling. In addition to providing higher performance, Serial I/O-based designs bring cost advantages over parallel implementations through fewer device pins, reduced board-space requirements, fewer PCB layers, easier layout of the PCB, and smaller connectors. Other advantages include reduced EMI and improved noise immunity.
"Serial connectivity is fast becoming a critical technology across a wide range of applications and markets," said Cary Snyder, a senior market analyst at Forward Concepts. "Demonstrating 10 Gbits/s technology is a major leap ahead for Xilinx over other PLD and ASIC suppliers, and enables the next wave of emerging serial standards."
"Xilinx's demonstration of 10 Gbits/s in silicon is a significant milestone in making high-speed serial connectivity accessible to all," commented Mark Pierpoint, vice president at Agilent Technologies. "Agilent is able to support Xilinx and their users with the broadest selection of test and measurement solutions that will help drive adoption throughout the industry."
This announcement is a direct result of Xilinx's vision and commitment to the importance of serial signaling technologies that led to the strategic acquisition of RocketChips, Inc. over two years ago. Today, the Communications Technology Division (formerly RocketChips) is focused solely on the creation and support of leading-edge multi-gigabit serial solutions.
Through its Serial Tsunami initiative, Xilinx has already delivered a wide range of solutions:

Virtex-II Pro Family—World's first platform FPGA with 622 Mbits/s to 3.125 Gbits/s serial transceivers.
First-to-market with proven intellectual property cores supporting key serial connectivity standards such as PCI Express"! and 1 and 10 Gbits/s Ethernet (XAUI).
Proven interoperability through demonstrations at key industry forums (e.g., PCI Express at Intel Developer's Forum, XAUI Group Test at University of New Hampshire Interoperability Lab).
New lightweight link-layer protocol, Aurora, along with supporting reference design.
Active leadership role in key industry-standards organizations, including PICMG, Serial RapidIO Trade Association, NPF (Network Processor Forum), OIF, PCI-SIG, and XFP.
Wealth of design resources, including development boards, design services, system design tools, and training.

Xilinx has really put a feather in its hat with this accomplishment. While several companies are showing parts and capabilities in the 5 Gbits/s range, only AMCC and Broadcom, according to Xilinx, are shipping CMOS parts that run at 10 Gbits/s. However, these devices are not for general interconnect, but are used to drive a laser diode.
It is additionally impressive that Xilinx was able to achieve the 10 Gbits/s result using a standard CMOS production process at UMC. The company claims that that the circuit was designed so that it can be migrated to other CMOS processes with different geometries.
To further emphasize its technical prowess, Xilinx stated that it intends to use the 10 Gbits/s circuitry in a product that will ship before the end of this year. It is likely that this will be a new FPGA produced using the 90 nm process that the company announced earlier this year.
The 10 Gbits/s signaling rate is needed for a number of standards that include 10 G Ethernet, OC-192, and 10G Fibre Channel. However, it is not at all clear as to how rapidly the 10 Gbits/s rate will be adopted for chip-to-chip and backplane applications. Xilinx might be better off developing an ASSP, rather than an FPGA, that combines four 3.125 Gbits/s signals to produce a 10 Gbits/s output.
In a related release, Cadence and Xilinx announced that the Xilinx RocketIO Design Kit for SPECCTRAQuest has been adopted by 500 designers. The design kit is used to simulate systems using the 3.125 Gbits/s I/Os in Xilinx Virtex-II Pro FPGAs. It is designed to address the PCB level simulation and implementation in gigahertz-speed systems.
The RocketIO Design Kit for SPECCTRAQuest design kit, which is provided free to Xilinx customers, allows engineers to develop constraints for their PCB systems. These constraints then drive the PCB floor planning, routing, and verification process. Cadence's SPECCTRAQuest Signal Integrity Expert tool starts at a price of $24,200 for a one-year license.

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