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NEC Selects Synplicity for Its ISSP ASICs

The manufacturer says . . . Murray Disman says . . .

NEC Electronics Selects Synplicity for Custom ASIC Synthesis Development
Synplicity to Deliver Custom Software to Enable Optimized Results for NEC's ISSP Products
MUNICH, Germany--March 4, 2003--Synplicity Inc., a leading supplier of software for the design and verification of semiconductors, announced it has signed a joint development agreement with NEC Electronics Corporation to provide support for NEC's Instant Silicon Solution Platform (ISSP) ASIC devices. Under terms of the agreement, Synplicity will develop custom synthesis mapping technology for its Synplify ASIC software, optimized to deliver the best performance, density, and design productivity for the ISSP devices. NEC Electronics has provided Synplicity with detailed information about its ISSP architecture, has validated the Synplify ASIC software's performance, and will integrate the software into its overall OpenCAD design flow. NEC Electronics and its subsidiaries in North America and Europe will offer library support for the custom Synplify ASIC software to its ISSP customers worldwide to enable high-performance, high-design capacity and fast turnaround times.
"We chose to work with Synplicity due to its synthesis expertise and history of success in developing custom mapping technology for the high-end FPGA market, and have found Synplicity to be a valuable and responsive development partner," said Dr. Hitoshi Yoshizawa, general manager, 3rd custom LSI division, NEC Electronics Corporation. "With a custom mapper optimized for our ISSP architecture, we expect our customers will be able to use the Synplify ASIC software to obtain the best timing performance possible. Likewise, we have found the Synplify ASIC software to be very easy to use not only by ASIC designers but also by system designers—a critical characteristic for tools in a high-productivity design flow—enabling our customers to realize the fast time-to-market benefits provided by our ISSP devices."
Ken McElvain, chief technical officer at Synplicity, said, "In order to realize the performance and time-to-market advantages offered by NEC's easy-to-design silicon platform, designers must have access to automated, easy-to-use design tools. Synplicity has consistently provided high-productivity, high-performance synthesis solutions, and the ISSP architecture is an ideal platform to apply our core synthesis and mapping capabilities. We teamed closely with NEC to understand the details of the unique ISSP architecture and develop a synthesis engine that would maximize the performance, density, and time-to-market advantages offered by the devices."
As part of this joint agreement, both parties intend to continue to optimize the Synplify ASIC software for the ISSP architecture. Synplicity also intends to train and work closely with NEC's field design centers in order to provide its mutual customers complete support. With the initial development complete, Synplicity and NEC Electronics expect customers will immediately realize timing performance, area, and run-time advantages over synthesis solutions that are not optimized for the ISSP devices. Synplicity intends to develop future releases of the Synplify ASIC software in conjunction with NEC Electronics to integrate the latest design software and architectural enhancements to the ISSP solution. Both companies will work with customers using ISSP devices to define additional design-flow advantages.
Pricing and Availability
The Synplify ASIC software version 2.4.1 with the ISSP-specific mapping technology is available from Synplicity now. A one-year time-based license starts at $45,000 (U.S.), and a perpetual license starts at $115,000 (U.S.). Customers on maintenance will be upgraded for no additional charge. The software is available for Linux (Red Hat 8.0), HP-UX 11.11, Sun Solaris 2.7/2.8/2.9, Windows NT 4.0, and Windows 2000 operating systems.

NEC has made a clever choice in selecting Synplicity's synthesis for the design of its Instant Silicon Solution Platform (ISSP) ASIC devices. FPGA design conversion is the primary market being pursued by NEC with its ISSP family of devices. Synplicity is a leading supplier of FPGA synthesis software, which should provide some degree of comfort to those designers converting their FPGA designs to the NEC ASIC.
According to NEC, ISSP devices are customizable using several upper metal layers to meet individual design requirements. An ISSP is ideal for mid-volume designers engaged in complex designs with high system clock speeds. However, the platforms are generally very easy to design, consume much lower power than a comparable FPGA-based solution, and offer lower NRE costs than cell-based designs.
NEC's first family of modular-array ISSPs (Instant Silicon Solution Platforms) is being produced using the its 0.13 µm UX4 process. This series contains three members with rated logic capacities of 227K, 530K, and 1109K gates. Each of the basic cells contains multiplexer-based logic and a register. The largest part in the series contains some 60K registers.
There are a number of other ASIC offerings that can be customized to a user's design with several metal layers. These are usually called modular arrays, a term introduced by Lightspeed Semiconductor. The makeup of the logic cells or modules are more complex than the basic gates used by LSI Logic.
Companies that offer modular-array ASICs include AMI Semiconductor, Chip Express, Lightspeed Semiconductor, and NEC Electronics. The HardCopy devices from Altera can be classified as modular arrays, but are only capable of converting designs for Altera FPGAs. AMI is making its XPressArray parts using a 0.18 µm process at TSMC. AMI customizes its devices with two metal layers that are applied in-house. Chip Express is now using a 0.25 µm process.
LSI Logic's RapidChip platform is also aimed at reducing NRE costs and long lead times, but for customers designing much more complex SOCs than those using the other modular array approaches. LSI's approach is to provide customers with a silicon platform that contains a substantial amount of application-specific embedded resources and a gate-array section (three to eight million ASIC gates capacity) that can be customized to a user's requirements with four metal layers.
The RapidChip platforms, like the other modular arrays, can be fabricated up to the final four metal layers and stocked for customer use. This clearly saves a good deal of time to first silicon, and results in reduced NRE mask charges. However, it is not clear as to how the much design and verification effort will be reduced.
LSI Logic's first RapidChip platform, StreamSlice, has 3 million gates for the users design, 2.6 MB of single-port SRAM, 650 KB of dual-port SRAM, and an 80-bit wide DDR SDRAM interface. Also embedded in the device are 36 HyperPHY I/Os interfaces that run at speed from 622 to 832 Mbits/s and 12 GigaBlaze I/Os that can support data rates ranging from 1.0625 to 3.2 Gbits/s.

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