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Xilinx Introduces v3.1 of System Generator for DSP

The manufacturer says . . . Murray Disman says . . .

Xilinx Slashes Simulation Time from Days to Minutes With Next-Generation Software Platform for High-Speed DSP Design
Industry-leading System Generator for DSP tool v3.1 adds new simulation capabilities supported by multiple DSP board suppliers.
SAN JOSE, Calif.--March 17, 2003--Xilinx, Inc., announced its next-generation System Generator for DSP tool v3.1—the industry's most popular DSP software platform for FPGAs. New capabilities such as "hardware-in-the-loop" and HDL cosimulation enable designers of ultra high speed DSP systems to save significant development costs by cutting simulation time from days to minutes. This announcement represents a major milestone in the Xilinx XtremeDSP initiative, and further extends the company's leadership position in high-performance DSP solutions. For complete information about the new tool and the XtremeDSP initiative, visit www.xilinx.com/dsp.
"On the whole, we think the System Generator for DSP tool is better than any competing DSP design methodology. For our applications, the high-level schematic design flow, powerful MatLAB visualization, and proven IP cores are very effective," said Chris Musial, engineering manager at Boeing SVS. "We are now able to generate and refine algorithmic designs in a fraction of the time that it took to hand code VHDL. We really think this is a winner for Boeing, especially given its cost."
Increased Productivity and Reduced Design Costs
The new System Generator for DSP tool radically reduces simulation time, and is the most cost-efficient FPGA-based DSP design methodology available on the market today. Internal benchmarks for designs running in "single-step mode" (hardware in lockstep with software simulation) have resulted in performance improvements from 7× to 43× faster than previous tool versions. Benchmarks for designs like bit-error rate (BER) testers controlled using free-running clocks have resulted in performance improvements up to six orders of magnitude.
The System Generator for DSP tool automatically translates DSP systems using The MathWork's MatLAB and Simulink tools into highly optimized VHDL and IP cores for Xilinx FPGAs. As a key component of the new System Generator for DSP tool, hardware-in-the-loop accelerates the design cycle significantly by allowing designers to verify designs in hardware directly from the Simulink environment. With other DSP design methodologies, designers are required to verify designs in multiple design environments—a complicated process resulting in significantly slower simulation times.
With hardware-in-the-loop, DSP engineers can verify designs running in hardware in "real time" to make design decisions and changes earlier in the design process. Hardware-in-the-loop is supported by a number of development-board vendors, including AlphaData, Annapolis, Lyr, and Nallatech, to provide designers with the choice to verify designs on their preferred hardware.
HDL cosimulation, another major component of the new System Generator for DSP tool, enables designers to import HDL legacy code. The new HDL cosimulation feature allows designers to reduce development cost and time by automatically allowing them to invoke Mentor Graphics' ModelSim tool directly from Simulink, and simulate their legacy HDL code together with new DSP models.
Additionally, the new tool enables designers to model the DSP system control plane through a subset of MathWorks' M-Code, logical, and Boolean expression blocks, and Xilinx's PicoBlaze soft microprocessor. The new control plane features optimize the design process by incorporating data-path and control-plane capabilities into a single environment. With the new control-plane capability, designers can model an entire DSP system within the familiar MatLAB/Simulink environment.
"Our DSP customers are enthusiastically adopting the System Generator based flow to FPGAs because it makes key design tasks so easy to accomplish," said Ken Karnofsky, DSP/communications marketing director at The MathWorks. "The inclusion of hardware-in-the-loop and cosimulation in the new version will significantly increase customers' productivity and further accelerate the appeal of Xilinx's DSP solution."
Xilinx Virtex-II Series Solutions Underpin XtremeDSP Initiative
This announcement is a direct result of Xilinx's commitment to the importance of DSP technology that resulted in the company's XtremeDSP initiative over two years ago.
Through its XtremeDSP initiative, Xilinx has already delivered a wide range of solutions:

Virtex-II Family—World's first platform FPGA with dedicated DSP features, including up to 556 embedded 18 × 18 multipliers and over 10 megabits block and distributed memory.
First to market with familiar DSP design methodologies resulting from strategic partnerships with The MathWorks, Mentor Graphics, and Cadence Design Systems.
Extensive library of proven DSP cores and advanced development boards to accelerate the design cycle and maximize performance.
Wealth of design resources, including development boards, design services, dedicated field specialists, and training.

Pricing and Availability
The new System Generator for DSP v3.1 is available now for use with Xilinx Virtex and Spartan Series FPGAs, and is priced at $1995. For more information about the new System Generator for DSP tool and the XtremeDSP solution, visit www.xilinx.com/systemgenerator_dsp.

Look at this—Xilinx seems to have just discovered that the verification of a hardware prototype of a DSP design can be run much faster than on a software-based simulator. FPGA-based hardware prototyping is a widely used method for the verification of ASICs and ASSPs. An additional advantage is the ability to begin software development early in the program.
The techniques used vary from the sophisticated systems supplied by Quickturn to the prototyping boards sold by some 50 vendors to a do-it-yourself approach where the user fabricates the board used to house the FPGA. This has been and still is a very lucrative market for Xilinx FPGAs since the largest available FPGAs are usually used for these prototypes. The prices for these parts, which are several thousand dollars each, are not a deterrent since only a limited number of devices is required.
Xilinx has adopted the hardware prototyping idea for the new "hardware-in-the-loop" feature in System Generator for DSP v3.1. To its credit, Xilinx has packaged a complex process into a simple pushbutton approach aimed at the DSP designer who has little FPGA design experience. The entire process—from synthesis, place and route, to the creation of the programming bitstream—is controlled by a user-initiated script contained in the tool.
Impressive, but not unexpected, gains in simulation speed are credited to the "hardware-in-the-loop" feature. The time required to run a simulation of a QAM Demodulator + extension was decreased from 1200 seconds to 18 seconds. In another run, the time required for the simulation of an additive white noise Gaussian channel design was decreased from 600 seconds to 80 seconds—hardly enough time to get a cup of coffee.
An API is used to access the four vendor boards that now support "hardware-in-the-loop." The API also allows designers to interface to their own target platforms. According to Xilinx, a free-running clock is provided to the hardware so that it is no longer running in lockstep with the software. The test is started and a flag is posted to indicate completion. The results from the FPGA run are then posted, and can be read in Simulink.
An interesting feature added to the control plane allows the user to get an estimate of the FPGA resources used by the design. The Resource Estimator screen shows the number of slices, FFs, blocks of RAM, LUTs, I/O Blocks, embedded multipliers, and tristate buffers required.

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