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Hier Design Promises Next-Generation FPGA Design Tools

The manufacturer says . . . Murray Disman says . . .

Hier Design Promises to Obsolete ASICs with Next-Generation EDA Software for FPGA Design Start-Up Staffed with EDA Veterans Set to Deliver FPGA Silicon Virtual-Prototyping Solution
SANTA CLARA, Calif.--March 17, 2003--Hier Design Inc., headquartered here, announced itself as an electronic design automation (EDA) industry newcomer intent on delivering software for high-speed, high-complexity field programmable gate array (FGPA) designs, a market overlooked by traditional EDA suppliers.
It is creating the next EDA beachhead by fueling the movement from application specific integrated circuits (ASICs) to FPGAs, and will launch software in July, 2003, to enable programmable devices to obsolete ASIC technology for most standard products.
"The vast majority of designers are creating boards and FPGAs, not ASICs and systems-on-a-chip," observes Jackson Kreiter, Hier Design's chief executive officer (CEO) and chairman. "The EDA industry has traditionally ignored this mainstream design community, creating a huge market opportunity for us."
Hier Design is building a company and product line to service the needs of the sophisticated FPGA designer community in a manner that will offer productivity and profitability, the underpinnings of a successful EDA company.
The Market
In recent years, FPGA design starts have shot past ASICs, largely due to their long-held time-to-market advantage. ASICs have become out of reach for an increasing number of product applications because of skyrocketing mask costs, prolonged time-to-manufacturing, risk of respins, and inventory costs. Roger Minear of Agere Systems, a speaker at this year's International Solid-State Circuits Conference (ISSCC), revealed that mask costs alone can range from $650,000 for 30 to 35 layers at 130 nm, with the cost jumping to $1,400,000 for 90 nm. Consequently, ASIC production volumes must be high before managers can justify their staggering expense.
Conversely, product applications for FPGAs have increased because of technology breakthroughs—10-million-gate density, 400 MHz clock speeds, embedded platform structures, and economical unit costs afforded by larger 300 mm wafer sizes. Simultaneously, the increased sophistication of FPGAs is driving the need for next-generation EDA design tools that can handle them.
EDA software has not kept pace with technological advancements in FPGA hardware. Today's designers are largely using last-generation software, created before deep-submicron technologies brought an explosion in gate count and interconnect delay dominance. The result is longer run times, numerous design iterations, a loss in performance, and an increasing gap between the programmable transistors available to designers and the average number they can use effectively. This gap undermines the primary FPGA advantage—time-to-market.
The Hier Design Solution
Hier Design will formally introduce its family of silicon virtual prototyping software for FPGAs in July, 2003. Its floor-planning and analysis software will be introduced first and will enable:

High-value, multi-million gate designs
Savings of $30,000 per design in labor costs
Savings of $500 per part per design
Time-to-market advantage

Early versions are currently in limited, pre-beta use with select customers. Products run on Windows, Linux, and Sun Solaris Unix-based workstations, and initially will support Xilinx devices only.

Hier Design was founded in August, 2001, by veterans from the ASIC side of the EDA industry. Their basic premise was that the tools used for FPGA design lagged behind the capabilities of the devices being developed. The company wants to bring the features found in modern ASIC design tools to the FPGA designer. In the past, it has taken several years for the features found in and the techniques used for ASIC design to make their way to the FPGA designer. Hier Design plans to accelerate this process.
The company has seen the growing importance of FPGAs, especially in the light of the escalating NREs and development costs associated with ASICs. It has also recognized the need for more sophisticated design tools as FPGAs have grown in size and complexity.
Hier's block-oriented floor-planning and analysis tool is in early evaluation at selected customers. The company expects to formally introduce the tool in July. The tool provides early estimates of timing and power consumption. It plans on following this tool with one for physical synthesis in 4Q03.
The claims for the floor-planning tool are that it reduces design iterations, increases performance, and reduces the area required for the design. In one instance, the company claims that the tool increased performance by 40%.
The first version of the tool works only with Xilinx's Virtex-II FPGAs. According to the company, this is because of the wide use of this family of FPGAs and not because Xilinx owns 15% of the new venture. Virtex-II is by far the most popular FPGA family, with much greater early acceptance than Xilinx's newer Virtex-II Pro family.

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