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Xilinx Moves V-II Pro to 300 mm

The manufacturer says . . . Murray Disman says . . .

Xilinx First to 130 nm 300 mm Production Qualification at UMC with Virtex-II Production
Xilinx customers benefit from direct path to lower cost 300 mm production qualification while others will endure risky re-qualification associated with 200 mm transition.
SAN JOSE, Calif.--March 28, 2003--Xilinx, Inc., the worlds leading provider of programmable solutions, announced production qualification for its industry-leading 130 nm Virtex-II Pro on 300 mm wafers with fab partner UMC at its most advanced manufacturing facility, Fab12a in Taiwan.
Xilinx is the first PLD provider to achieve this industry milestone. The company's strategy to deploy 130 nm CMOS technology on 300 mm wafers will greatly benefit its customer base by providing a proven-cost reduction path without the need for re-qualification. Xilinx leads the industry in 300 mm production, and attributes its success to its dual-fab strategy and close relationships with fab partners IBM and UMC. The 300 mm wafer process offers improved defect densities, and hence better yields, as well as approximately 2.5 times the amount of gross die per wafer relative to 200 mm processes. The company's aggressive move to 300 mm began with its commitment to provide customers with the fastest possible cost-reduction path.
"We've always considered 300 mm production as a necessary component of our manufacturing strategy and a necessary step in ensuring customer satisfaction," said Wim Roelandts, president and CEO at Xilinx. "300 mm provides the lowest cost of manufacture, lowest defect density, and most advanced high-volume process technology options. Going forward, all Xilinx products will go directly into production on the more cost-effective 300 mm wafers."
"300 mm is a must have in today's uncertain economy—cost-effective manufacture is paramount, and 300 mm is the only way for semiconductor suppliers to stay competitive," said Rich Sevcik, senior vice president and general manager of the Programmable Logic Systems Group at Xilinx. "Suppliers who have chosen to standardize on 200 mm need to catch up and make the move to 300 mm in order to reduce costs. The problem is that once they make the necessary move, their customers will suffer by enduring a painful re-qualification process."
Fu Tai Liou, president of the America Business Group at UMC, stated, "This product qualification milestone proves conclusively that Xilinx is the dominant force in the deployment of advanced process technologies for programmable-logic devices. Xilinx's continued success is clearly a by-product of an unwavering commitment to customer satisfaction. UMC is honored to be working hand-in-hand with Xilinx to enable the timely delivery of excellent products that fully leverage the performance and cost benefits of the world's most advanced production technologies."
The Xilinx Virtex-II Pro family is the world's first and only FPGA to offer integrated PowerPC embedded technology and 3.125 Gbits/s serial transceivers. Virtex-II Pro devices include these multiple PowerPC CPUs and multi-gigabit serial transceivers at no additional charge, providing unequaled capability and value for today's system design requirements.

The other interesting bit of news is that Xilinx is now producing all of its advanced products, which includes the 130 nm Virtex-II Pro, on 300 mm wafers. Both IBM and UMC are mentioned in Xilinx's release, but only UMC has issued a press release confirming that it is producing the 130 nm Virtex-II Pro on 300 mm wafers.
Xilinx issued the accompanying press release stating it has achieved production qualification for its 130 nm Virtex-II Pro on 300 mm wafers with fab partner UMC. These parts are being produced using FSG as the dielectric material.
V-II Pro was first sampled well over a year ago. It seems that Xilinx has not been able to qualify the family and move it into its distributor channels because of problems with IBM's and UMC's SiLK-based copper interconnect process. Xilinx is now ramping production of the parts using FSG, and expects to have them to their distributors before the end of this quarter.
Xilinx has stated that their production on 300 mm wafers is already more economical, on the basis of the cost of a good die, than on 200 mm wafers. This is at odds with other industry and market research estimates that the cost break-even point between 200 mm and 300 mm wafers will be reached at the end of 2003. Xilinx seems to be way ahead of the rest of the semiconductor industry in reaping the benefits of 300 mm wafer production.
The company also claims that it planned for both FSG and low-k dielectrics for its 130 nm Virtex-II Pro and its new 90 nm family. Xilinx says that it set up its speed files to accommodate the two different dielectric types without a speed penalty. This is all very hard to digest, and it is very likely that the fastest speed grade for the V-II Pro will be increasingly difficult to get as the company transitions to FSG for these FPGAs.
The claim that these is little performance difference between V-II Pro parts built with FSG, with a dielectric constant of 3.8, and SiLK, with a dielectric constant of 2.8, is difficult to accept. It is true that the major part of the interconnect delay comes from the switching transistors in the signal path. However, the additional capacitance introduced with FSG will increase delays in some paths that can be critical in certain designs.
The growth of the FPGA business has been and still is highly dependent on the evolution of process technologies. At 130 nm and below we are entering an area where ASICs can only be justified for very high-volume applications. Both Altera and Xilinx recognize this trend, and both are committed to use the most advanced technologies available.
Altera tends to be somewhat more conservative than Xilinx is process adoption. This worked to its advantage at 130 nm where it has introduced three different families and has moved these into production. Xilinx is only now in production at 130 nm with a single family. On the other hand, Xilinx is far ahead of Altera in the move to 90 nm and 300 mm wafers.

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