Programmable Logic

Product Review

Archives | Feedback

TSMC Claims 130 nm Lead

The manufacturer says . . . Murray Disman says . . .

TSMC Leads Industry in Production of 0.13 µm FSG and Low-k Products
High-Volume Manufacturer of Advanced-Technology Semiconductors Also Pushes 90 nm Performance Barriers
HSINCHU, Taiwan,and SAN JOSE Calif.--April 16, 2003--Taiwan Semiconductor Manufacturing Company announced new production data on its 0.13 µm processes as well as its status for the 90 nm process.
With more than 230 product designs taped out to its 0.13 µm processes, and more than 100 thousand 0.13 µm wafers shipped to date, TSMC leads the industry in advanced-technology volume production. Furthermore, TSMC's 0.13 µm low-k process technology is the first in the foundry industry to pass customer product qualifications and enter volume production.
On the 90 nm front, TSMC has recorded more than 20 customer projects that are at various design stages. Production for customers using TSMC's Nexsys 90 nm technology with copper and low-k dielectrics on more cost-competitive 300 mm wafers is expected to start in the third quarter of 2003.
"The successful ramp of our 0.13 µm process technology for use by customers in a wide variety of market segments, and the recent availability of our Nexsys 90 nm process are examples of realizing TSMC's vision: To be the most advanced, innovative, and largest provider of foundry services, and in partnership with our customers, to forge a most powerful force in the semiconductor industry," said Dr. Rick Tsai, president and COO of TSMC.
"To realize this vision, we must be a technology leader, competitive with other industry leaders," continued Dr. Tsai. "Just as important, we must be the manufacturing leader, with the best reputation, best services, and greatest total-benefits to our customers. What we have achieved in the past creates solid foundation for TSMC to go after this vision."
The 230-plus 0.13 µm customer design tapeouts span products in the consumer, computer, and communications markets. TSMC anticipates shipping more than 400,000 eight-inch equivalent wafers in 0.13 µm technology this year. By the end of 2003, the monthly installed capacity for 0.13 µm technology at TSMC Fab 12, a 300-mm-wafer fab, is expected to reach approximately half of TSMC's total monthly installed capacity for 0.13 µm technology. The company expects 20 percent of its revenues will come from 0.13 µm products in 2003.
"There is a big difference between having the capability to demonstrate novel semiconductor technology and being able to produce in a manufacturing line with good yields," said Genda Hu, vice president of marketing for TSMC. "TSMC has consistently demonstrated two of our core strengths: delivering a highly manufacturable process to our customers, and supporting that process with customer-oriented services. TSMC has taken a noticeable lead in both areas for 0.13 µm node. Furthermore, with the success of our volume production and product qualification of the low-k dielectric process, we fully anticipate similar success at 90 nm and beyond."
TSMC's multiple process options for the 0.13 µm and Nexsys 90 nm technologies will be presented at TSMC 2003 Technology symposia held in North America, Asia, and Europe. The first symposium will be held in San Jose, California, on April 22.
TSMC Low-k Status
A number of companies are using TSMC's low-k, 0.13 µm technology in volume production, two of which, LSI Logic and Agere Systems, have announced product qualification. In addition, packaging vendors ASE and Amkor have collaborated extensively with TSMC and qualified their packages for the 0.13 µm low-k process.
The advantage of low-k dielectrics is significant for certain designs. Agere Systems, which recently announced that it is using TSMC's low-k based 0.13 µm process for its DSP16411 digital signal processor (DSP) chips, now in volume production, has reported a performance improvement of 20 percent and a power savings of another 20 percent compared to competitor chips without the low-k technology.
TSMC 90 nm Status
TSMC acknowledges that, to date, more than twenty 90 nm customer projects are at various design stages. Fully functional 90 nm test chips were successfully produced in the fourth quarter of 2001. Production for customers using TSMC's Nexsys 90 nm technology with copper and low-k dielectrics on more cost-competitive 300 mm wafers is expected to start in the third quarter of 2003.
Other notable milestones of TSMC's 90 nm process development include:

The delivery of 90 nm design rules to key EDA Alliance members in 2001
Early validation of Library and IP Alliance member products in 2002
Multiple customer designs verified with TSMC's CyberShuttle service to date

TSMC and UMC are in the midst of some frantic PR efforts about who can claim process leadership. This is important to programmable logic since TSMC is Altera's fab, and UMC/IBM are Xilinx's fabs.
Xilinx's release of its 90 nm Spartan-3 family and the announcement that it is finally in qualified production of the Virtex-II Pro series at UMC on 300 mm wafers gives Xilinx the edge in process leadership. Until these two announcements, Altera held the leadership position since it was shipping several 130 nm FPGAs from qualified production lines while Xilinx did not have any qualified 130 nm parts in production. The inability to get Virtex-II Pro into Xilinx's distribution channels gave Altera room and time to establish its Stratix and Cyclone product lines. The 90 nm Spartan-3 is aimed at both the 130 nm Stratix and Cyclone Altera families.
UMC seems farther along in regards to 300 mm production at 130 nm than either TSMC or IBM. TSMC does lead in terms of the volume of devices produced at 130 nm and the production of low-k parts at this node. Neither IBM nor UMC have yet announced a qualified low-k process.
IBM and UMC are both delivering samples of Xilinx's 90 nm Spartan-3. According to Xilinx, both fabs are shipping parts made on 200 mm wafers using FSG or low-k dielectrics. Xilinx plans to move some Spartan-3 parts to production on 300 mm wafers with, presumably, a low-k dielectric before the end of this year. TSMC now says it will be in production at 90 nm with 300 mm wafers and a low-k dielectric during 3Q03.
The 90 nm ball is now in Altera's court. The company has said that it will be in production with 90 nm parts with a low-k dielectric during 1H04. It may now feel pressured to act sooner to counter Xilinx's Spartan-3 release.
Altera has announced that it plans to transition the 130 nm Stratix device family to 300 mm wafers during the second half of 2003. Cyclone and Stratix GX device families will be migrated early in 2004. On the other hand, Xilinx says that Virtex-II Pro, Virtex-II, and Virtex-E have transitioned almost entirely to 300 mm wafers, providing the company with claimed cost reductions of more than 30%.
Altera, in a snipe at Xilinx, has said that "Customers will receive complete details on the transition of the Stratix device family to 300 mm wafers. This will include a process change notification (PCN) to customers, qualification and reliability data, and a white paper summarizing the process differences, ordering information, and a detailed production schedule."

Click here to get your listing up.