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Lattice Claims Programmable SerDes Leadership

The manufacturer says . . . Murray Disman says . . .

Lattice Semiconductor Extends Programmable SerDes Leadership with Introduction of 4-Channel Field-Programmable System Chip Device
ORT42G5 FPSC offers 4 channels of 3.7 Gbits/s SerDes plus over 10,000 logic elements in small-footprint BGA package.
HILLSBORO, Ore.--April 14, 2003--Lattice Semiconductor Corporation, the leader in programmable SerDes technology, announced the availability of the ORT42G5, a Field-Programmable System Chip (FPSC) incorporating four SerDes channels, each running at 0.6 to 3.7 Gbits/s, plus embedded 8b/10b encoding, XAUI and FibreChannel link state machines, and over 10,000 FPGA logic elements, all in a compact 484 fine-pitch BGA package. The device is targeted at high-speed chip-to-chip and backplane applications such as 10 Gigabit Ethernet, 1 Gigabit and 2 Gigabit FibreChannel, and 10 Gigabit FibreChannel for the rapidly expanding 10 Gigabit storage area networking market.
"With the introduction of the ORT42G5, Lattice is extending its leadership position in the programmable SerDes market," said Stan Kopec, vice president of corporate marketing at Lattice. "Our portfolio of SerDes-based devices is already the broadest in the industry, and the ORT42G5 offers a cost-effective device that will save designers board space and reduce trace routing and complexity. We've packed 4 channels of the industry's fastest production SerDes along with plenty of programmable logic for bridging and proprietary packet-processing functions. The competition requires at least two chips to accomplish what we can do in a compact 23 × 23 mm footprint," Kopec added.
Lattice's FPSC devices are high-performance programmable devices that combine optimized embedded core functions together with flexible, general-purpose FPGA logic. In addition to its four SerDes channels and over 10,000 ORCA FPGA logic elements for general-purpose logic, the ORT42G5 includes fully embedded 8b/10b encoding, XAUI and FibreChannel link state machines, and multi-channel alignment capabilities.
The SerDes on the ORT42G5 includes numerous best-in-class features:

3.7—0.6 Gbits/s operating range per channel
<225 mW per channel worst case at 3.125 Gbits/s
Transmit jitter of 0.17 UI at 3.125 Gbits/s
Receive jitter of 0.75 UI at 3.125 Gbits/s
Drives at least 40" (1 m) of FR-4 backplane at 3.125 Gbits/s
Fast Locking Times with bit realignment at 300 ns (938 bit times @ 3.125 Gbits/s)

The device also features 204 programmable user I/Os supporting a variety of advanced interface standards including LVCMOS, LVTTL, LVDS, Bus-LVDS, LVPECL, HSTL, SSTL3/2, GTL, GTL+, ZBT, and DDR to facilitate easy interfacing. Another FPSC device in the Lattice backplane portfolio, the ORT82G5, offers eight channels of the same SerDes core.
To document the superior characteristics of its SerDes technology, Lattice has just released the second edition of its SerDes Handbook. This handbook provides actual data on the typical eye diagrams, jitter, lock time, and other key operational aspects of the SerDes technology used in the ORT42G5 and ORT82G5 FPSCs, as well as information on its ORSO82G5, ORT8850, ispGDX2, and ispXPGA product families. It is available in electronic form on the Lattice Web site.
Availability
The ORT42G5-484PBGAM FPSC is currently available, with production quantities available Q3 2003. Volume pricing the second half of 2004 in quantities of 10,000 is $80.00. The device is supported by Lattice's ispLEVER v3.0 design software, a dedicated design kit, and popular third-party synthesis, simulation, and verification tools.

Lucent, before the acquisition of its FPGA business by Lattice, was the first to deliver a 3.125 Gbits/s I/O capability married to an FPGA. Lattice now finds itself competing with Xilinx's Virtex-II Pro and Altera's Stratix GX. The ability of the ORT42G5 to run at 3.7 Gbits/s will help Lattice distance itself from the competition, especially in chip-to-chip and backplane applications.
The ORT42G5 was derived from Lattice's ORT84G5, which contains eight 3.7 Gbits/s I/Os. The company claims that performance ranging from 0.6 to 3.7 Gbits/s has been demonstrated over 26" of FR-4 backplane and at 3.125 Gbits/s over 40" of FR-4 backplane over the voltage and temperature ranges specified. The device is being produced using a 160 nm process, and internal speeds in excess of 250 MHz are claimed for the part.
The FPGA portions of Xilinx's Virtex-II Pro and Altera's Stratix GX devices are more modern designs than the ORCA in the ORT42G5, and are made on more advanced 130 nm processes. The Stratix GX devices now being shipped contain more than twice as many logic elements as the Lattice parts, and either 4, 8, or 16 3.125 Gbits/s I/Os.
Virtex-II Pro is finally in production at UMC. The family contains 10 parts with capacities ranging from 3K to 125K logic cells. The number of 3.125 Gbits/s I/Os contained ranges from 4 to 24.

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